Intel DG965MQ DG965MQ Technical Product Specification - Page 49

PCI Interrupt Routing Map

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Technical Reference 2.6 PCI Interrupt Routing Map This section describes interrupt sharing and how the interrupt signals are connected between the PCI bus connectors and onboard PCI devices. The PCI specification specifies how interrupts can be shared between devices attached to the PCI bus. In most cases, the small amount of latency added by interrupt sharing does not affect the operation or throughput of the devices. In some special cases where maximum performance is needed from a device, a PCI device should not share an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt with a PCI add-in card. PCI devices are categorized as follows to specify their interrupt grouping: • INTA: By default, all add-in cards that require only one interrupt are in this category. For almost all cards that require more than one interrupt, the first interrupt on the card is also classified as INTA. • INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is classified as INTB. (This is not an absolute requirement.) • INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a fourth interrupt is classified as INTD. The ICH8 has eight Programmable Interrupt Request (PIRQ) input signals. All PCI interrupt sources either onboard or from a PCI add-in card connect to one of these PIRQ signals. Some PCI interrupt sources are electrically tied together on the board and therefore share the same interrupt. Table 17 shows an example of how the PIRQ signals are routed. Table 17. PCI Interrupt Routing Map PCI Interrupt Source ICH8 PIRQ Signal Name PIRQA PIRQB PIRQC PIRQD PIRQE PIRQF PIRQG PIRQH ICH8 LAN INTA PCI bus connector 1 INTD INTA INTB INTC PCI bus connector 2 INTC INTB INTA INTD IEEE-1394a controller INTA NOTE In PIC mode, the ICH8 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 16 for the allocation of PIRQ lines to IRQ signals in APIC mode. PCI interrupt assignments to USB ports, Serial ATA ports, and PCI Express ports are dynamic. 49

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Technical Reference
49
2.6
PCI Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected
between the PCI bus connectors and onboard PCI devices.
The PCI specification
specifies how interrupts can be shared between devices attached to the PCI bus.
In
most cases, the small amount of latency added by interrupt sharing does not affect
the operation or throughput of the devices.
In some special cases where maximum
performance is needed from a device, a PCI device should not share an interrupt with
other PCI devices.
Use the following information to avoid sharing an interrupt with a
PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
•
INTA:
By default, all add-in cards that require only one interrupt are in this
category.
For almost all cards that require more than one interrupt, the first
interrupt on the card is also classified as INTA.
•
INTB:
Generally, the second interrupt on add-in cards that require two or more
interrupts is classified as INTB.
(This is not an absolute requirement.)
•
INTC and INTD:
Generally, a third interrupt on add-in cards is classified as INTC
and a fourth interrupt is classified as INTD.
The ICH8 has eight Programmable Interrupt Request (PIRQ) input signals.
All PCI
interrupt sources either onboard or from a PCI add-in card connect to one of these
PIRQ signals.
Some PCI interrupt sources are electrically tied together on the board
and therefore share the same interrupt.
Table 17 shows an example of how the
PIRQ signals are routed.
Table 17. PCI Interrupt Routing Map
ICH8 PIRQ Signal Name
PCI Interrupt Source
PIRQA
PIRQB
PIRQC
PIRQD
PIRQE
PIRQF
PIRQG
PIRQH
ICH8 LAN
INTA
PCI bus connector 1
INTD
INTA
INTB
INTC
PCI bus connector 2
INTC
INTB
INTA
INTD
IEEE-1394a controller
INTA
±
NOTE
In PIC mode, the ICH8 can connect each PIRQ line internally to one of the IRQ signals
(3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a
PIRQ line will have a unique interrupt.
However, in certain interrupt-constrained
situations, it is possible for two or more of the PIRQ lines to be connected to the same
IRQ signal.
Refer to Table 16 for the allocation of PIRQ lines to IRQ signals in APIC
mode.
PCI interrupt assignments to USB ports, Serial ATA ports, and PCI Express ports are
dynamic.