Intel E6300 Data Sheet - Page 30

Electrical Specifications Table 18. FSB Differential Clock Specifications (800 MHz FSB) T# Parameter Min Nom Max Unit Figure Notes1 BCLK[1:0] Frequency 198.980 - 200.020 MHz - 2 T1: BCLK[1:0] Period 4.99950 - 5.00050 ns 3 3 T2: BCLK[1:0] Period Stability - - 150 ps 3 4 T5: BCLK[1:0] Rise and Fall Slew Rate 2.5 - 8 V/nS 3 5 T6: Slew Rate Matching N/A N/A 20 % 6 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a 200 MHz BCLK[1:0]. 2. Duty Cycle (High time/Period) must be between 40 and 60%. 3. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2). Min period specification is based on -300 PPM deviation from a 5 ns period. Max period specification is based on the summation of +300 PPM deviation from a 5 ns period and a +0.5% maximum variance due to spread spectrum clocking. 4. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability. 5. Measurement taken from differential waveform. 6. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75 mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. Slew rate matching is a single ended measurement. Table 19. FSB Differential Clock Specifications (1066 MHz FSB) T# Parameter BCLK[1:0] Frequency T1: BCLK[1:0] Period T2: BCLK[1:0] Period Stability T5: BCLK[1:0] Rise and Fall Slew Rate Slew Rate Matching Min 265.307 3.74963 2.5 N/A Nom - N/A Max 266.693 3.76922 150 8 20 Unit MHz ns ps V/ns % Figure 3 3 4 - Notes1 6 2 3 4 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a 266 MHz BCLK[1:0]. 2. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2). The Min period specification is based on -300 PPM deviation from a 3.75 ns period. The Max period specification is based on the summation of +300 PPM deviation from a 3.75 ns period and a +0.5% maximum variance due to spread spectrum clocking. 3. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability. 4. Slew rate is measured through the VSWING voltage range centered about differential zero. Measurement taken from differential waveform. 5. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75 mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 6. Duty Cycle (High time/Period) must be between 40% and 60% 30 Datasheet