Intel E6300 Data Sheet - Page 86

Features Figure 18. Processor Low Power State Machine Normal State - Normal Execution HALT or MWAIT Instruction and HALT Bus Cycle Generated INIT#, INTR, NMI, SMI#, RESET#, FSB interrupts Extended HALT or HALT State - BCLK running - Snoops and interrupts allowed STPCLK# STPCLK# Asserted De-asserted Stop Grant State - BCLK running - Snoops and interrupts allowed STPCLK# Asserted STPCLK# De-asserted Snoop Event Occurs Snoop Event Serviced Snoop Event Occurs Snoop Event Serviced Extended HALT Snoop or HALT Snoop State - BCLK running - Service Snoops to caches Extended Stop Grant or Stop Grant Snoop State - BCLK running - Service Snoops to caches SLP# Asserted SLP# De-asserted Sleep State - BCLK running - No Snoops or interrupts allowed - PECI unavailable in this state DPSLP# Asserted DPSLP# De-asserted Deep Sleep State - BCLK can be stopped - No Snoops or interrupts allowed - PECI unavailable in this state DPRSTP# Asserted DPRSTP# De-asserted Deeper Sleep State - BCLK can be stopped - No Snoops or interrupts allowed - PECI unavailable in this state 6.2.1 6.2.2 6.2.2.1 Normal State This is the normal operating state for the processor. HALT and Extended HALT Powerdown States The processor supports the HALT or Extended HALT powerdown state. The Extended HALT powerdown state must be configured and enabled using the BIOS for the processor to remain within specification. The Extended HALT state is a lower power state as compared to the Stop Grant State. If Extended HALT is not enabled, the default powerdown state entered will be HALT. See the following sections for details about the HALT and Extended HALT states. HALT Powerdown State HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted; however, the other processor continues normal operation. The halted core will transition to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# causes the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT powerdown state. See the Intel Architecture Software Developer's Manual, Volume 3B: System Programming Guide, Part 2 for more information. 86 Datasheet