Intel E6320 Specification Update - Page 14

Errata (Sheet 5 of 5) Number Steppings D-2 Q-0 Status BJ111 X X No Fix BJ112 X X No Fix BJ113 X X No Fix BJ114 X X No Fix BJ115 X X No Fix BJ116 X X No Fix BJ117 X X No Fix BJ118 X X No Fix BJ119 X X No Fix BJ120 X BJ121 X BJ122 X BJ123 X BJ124 X BJ125 X BJ126 X BJ127 X BJ128 X X No Fix X No Fix X Plan Fix X No Fix X No Fix X No Fix X No Fix X No Fix X No Fix ERRATA VM Exits Due to "NMI-Window Exiting" May Not Occur Following a VM Entry to the Shutdown State Execution of INVVPID Outside 64-Bit Mode Cannot Invalidate Translations For 64Bit Linear Addresses VEX.L is Not Ignored with VCVT*2SI Instructions MCI_ADDR May be Incorrect For Cache Parity Errors Instruction Fetches Page-Table Walks May be Made Speculatively to Uncacheable Memory Reported Maximum Memory Frequency Capability May Be Higher Than Expected The Processor May Not Properly Execute Code Modified Using A Floating-Point Store Execution of GETSEC[SEXIT] May Cause a Debug Exception to be Lost VM Exits Due to GETSEC May Save an Incorrect Value for "Blocking by STI" in the Context of Probe-Mode Redirection Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior IA32_MC5_CTL2 is Not Cleared by a Warm Reset Performance Monitor Counters May Produce Incorrect Results The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error is Logged Spurious Intel® VT-d Interrupts May Occur When the PFO Bit is Set Processor May Livelock During On Demand Clock Modulation The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging EPT Violations May Report Bits 11:0 of Guest Linear Address Incorrectly IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The Highest Index Value Used For VMCS Encoding Specification Changes Number SPECIFICATION CHANGES None for this revision of this specification update. Specification Clarifications Number SPECIFICATION CLARIFICATIONS None for this revision of this specification update. 14 Specification Update