Intel E6320 Specification Update - Page 39

MSR_Temperature_Target May Have an Incorrect Value in - service manual

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Page 39 highlights

 BJ59. XSAVE Executed During Paging-Structure Modification May Cause Unexpected Processor Behavior Problem: Execution of XSAVE may result in unexpected behavior if the XSAVE instruction writes to a page while another logical processor clears the dirty flag or the accessed flag in any paging-structure entry that maps that page. Implication: This erratum may cause unpredictable system behavior. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. BJ60. C-state Exit Latencies May be Higher Than Expected Problem: Core C-state exit can be delayed if a P-state transition is requested before the pending C-state exit request is completed. Under certain internal conditions the core C-state exit latencies may be over twice the value specified in the Intel® 64 and IA-32 Architectures Optimization Reference Manual. Implication: While typical exit latencies are not impacted, the worst case core C-state exit latency may be over twice the value specified in the Intel® 64 and IA-32 Architectures Optimization Reference Manual and may lead to a delay in servicing interrupts. Intel has not observed any system failures due to this erratum. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. BJ61. MSR_Temperature_Target May Have an Incorrect Value in the Temperature Control Offset Field Problem: Under certain conditions the value in MSR_Temperature_Target (1A2H) bits [15:8] (Temperature Control Offset) may indicate a temperature up to 25 degrees higher than intended. Implication: Due to this erratum, fan speed control algorithms that rely on this value may not function as expected Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Specification Update 39

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Specification Update
39
BJ59.
XSAVE Executed During Paging-Structure Modification May Cause
Unexpected Processor Behavior
Problem:
Execution of XSAVE may result in unexpected behavior if the XSAVE instruction writes
to a page while another logical processor clears the dirty flag or the accessed flag in
any paging-structure entry that maps that page.
Implication:
This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially available software.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ60.
C-state Exit Latencies May be Higher Than Expected
Problem:
Core C-state exit can be delayed if a P-state transition is requested before the pending
C-state exit request is completed. Under certain internal conditions the core C-state
exit latencies may be over twice the value specified in the Intel
®
64 and IA-32
Architectures Optimization Reference Manual.
Implication:
While typical exit latencies are not impacted, the worst case core C-state exit latency
may be over twice the value specified in the Intel
®
64 and IA-32 Architectures
Optimization Reference Manual and may lead to a delay in servicing interrupts. Intel
has not observed any system failures due to this erratum.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ61.
MSR_Temperature_Target May Have an Incorrect Value in the
Temperature Control Offset Field
Problem:
Under certain conditions the value in MSR_Temperature_Target (1A2H) bits [15:8]
(Temperature Control Offset) may indicate a temperature up to 25 degrees higher than
intended.
Implication:
Due to this erratum, fan speed control algorithms that rely on this value may not
function as expected
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.