Intel E6320 Specification Update - Page 34

Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value

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Page 34 highlights

BJ44. Problem: VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported Field in VMCS The Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2B states that execution of VMREAD or VMWRITE should fail if the value of the instruction's register source operand corresponds to an unsupported field in the VMCS (Virtual Machine Control Structure). The correct operation is that the logical processor will set the ZF (Zero Flag), write 0CH into the VM-instruction error field and for VMREAD leave the instruction's destination operand unmodified. Due to this erratum, the instruction may instead clear the ZF, leave the VM-instruction error field unmodified and for VMREAD modify the contents of its destination operand. Implication: Accessing an unsupported field in VMCS will fail to properly report an error. In addition, VMREAD from an unsupported VMCS field may unexpectedly change its destination operand. Intel has not observed this erratum with any commercially available software. Workaround: Software should avoid accessing unsupported fields in a VMCS. Status: For the steppings affected, see the Summary Tables of Changes. BJ45. Clock Modulation Duty Cycle Cannot be Programmed to 6.25% Problem: When programming field T_STATE_REQ of the IA32_CLOCK_MODULATION MSR (19AH) bits [3:0] to '0001, the actual clock modulation duty cycle will be 12.5% instead of the expected 6.25% ratio. Implication: Due to this erratum, it is not possible to program the clock modulation to a 6.25% duty cycle. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ46. Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX.vvvv May Produce a #NM Exception Problem: The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (Invalid- Opcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to this erratum, if CR0.TS is "1", the processor may instead produce a #NM (Device-NotAvailable) exception. Implication: Due to this erratum, some undefined instruction encodings may produce a #NM instead of a #UD exception. Workaround: Software should always set the vvvv field of the VEX prefix to 1111b for instances of the VAESIMC and VAESKEYGENASSIST instructions. Status: For the steppings affected, see the Summary Tables of Changes. 34 Specification Update

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34
Specification Update
BJ44.
VMREAD/VMWRITE Instruction May Not Fail When Accessing an
Unsupported Field in VMCS
Problem:
The Intel
®
64 and IA-32 Architectures Software Developer's Manual, Volume 2B states
that execution of VMREAD or VMWRITE should fail if the value of the instruction's
register source operand corresponds to an unsupported field in the VMCS (Virtual
Machine Control Structure). The correct operation is that the logical processor will set
the ZF (Zero Flag), write 0CH into the VM-instruction error field and for VMREAD leave
the instruction's destination operand unmodified. Due to this erratum, the instruction
may instead clear the ZF, leave the VM-instruction error field unmodified and for
VMREAD modify the contents of its destination operand.
Implication:
Accessing an unsupported field in VMCS will fail to properly report an error. In addition,
VMREAD from an unsupported VMCS field may unexpectedly change its destination
operand. Intel has not observed this erratum with any commercially available software.
Workaround:
Software should avoid accessing unsupported fields in a VMCS.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ45.
Clock Modulation Duty Cycle Cannot be Programmed to 6.25%
Problem:
When programming field T_STATE_REQ of the IA32_CLOCK_MODULATION MSR (19AH)
bits [3:0] to '0001, the actual clock modulation duty cycle will be 12.5% instead of the
expected 6.25% ratio.
Implication:
Due to this erratum, it is not possible to program the clock modulation to a 6.25% duty
cycle.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ46.
Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value
for VEX.vvvv May Produce a #NM Exception
Problem:
The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (Invalid-
Opcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to
this erratum, if CR0.TS is “1”, the processor may instead produce a #NM (Device-Not-
Available) exception.
Implication:
Due to this erratum, some undefined instruction encodings may produce a #NM instead
of a #UD exception.
Workaround:
Software should always set the vvvv field of the VEX prefix to 1111b for instances of
the VAESIMC and VAESKEYGENASSIST instructions.
Status:
For the steppings affected, see the Summary Tables of Changes.