Intel E6320 Specification Update - Page 40

L1 Data Cache Errors May be Logged With Level Set to 1 Instead of 0

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Page 40 highlights

BJ62. Intel® VT-d Interrupt Remapping Will Not Report a Fault if Interrupt Index Exceeds FFFFH Problem: With Intel VT-d (Virtualization Technology for Directed I/O) interrupt remapping, if subhandle valid (bit 3) is set in the address of an interrupt request, the interrupt index is computed as the sum of the interrupt request's handle and subhandle. If the sum is greater than FFFFH (the maximum possible interrupt-remapping table size), a remapping fault with fault reason 21H should be reported. Due to this erratum, this condition is not reported as a fault. Instead, the low 16 bits of the sum are erroneously used as an interrupt index to access the interrupt-remapping table. Implication: If the interrupt index of an interrupt request exceeds FFFFH, a remapping fault with fault reason 21H is not reported and, instead, the request uses the IRTE (interruptremapping table entry) indexed by the low 16 bits of the interrupt index. Workaround: Software can use requestor-id verification to block the interrupts that would be delivered due to this erratum. Interrupts blocked in this way produce a remapping fault with fault reason 26H. Status: For the steppings affected, see the Summary Tables of Changes. BJ63. PCIe* Link Speed May Not Change From 5.0 GT/s to 2.5 GT/s Problem: If a PCI Express device changes its supported PCIe link speed from 5.0 GT/s to 2.5 GT/ s without initiating a speed change request and subsequently the L1 power management mode is entered, further retrains initiated by software will not change speed to 2.5 GT/s. Implication: Intel has not observed any PCI Express device that changes supported link speed without actually initiating a speed change. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ64. L1 Data Cache Errors May be Logged With Level Set to 1 Instead of 0 Problem: When an L1 Data Cache error is logged in IA32_MCi_STATUS[15:0], which is the MCA Error Code Field, with a cache error type of the format 0000 0001 RRRR TTLL, the LL field may be incorrectly encoded as 01 instead of 00. Implication: An error in the L1 Data Cache may report the same LL value as the L2 Cache. Software should not assume that an LL value of 01 is the L2 Cache. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 40 Specification Update

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40
Specification Update
BJ62.
Intel
®
VT-d Interrupt Remapping Will Not Report a Fault if Interrupt
Index Exceeds FFFFH
Problem:
With Intel VT-d (Virtualization Technology for Directed I/O) interrupt remapping, if
subhandle valid (bit 3) is set in the address of an interrupt request, the interrupt index
is computed as the sum of the interrupt request’s handle and subhandle. If the sum is
greater than FFFFH (the maximum possible interrupt-remapping table size), a
remapping fault with fault reason 21H should be reported. Due to this erratum, this
condition is not reported as a fault. Instead, the low 16 bits of the sum are erroneously
used as an interrupt index to access the interrupt-remapping table.
Implication:
If the interrupt index of an interrupt request exceeds FFFFH, a remapping fault with
fault reason 21H is not reported and, instead, the request uses the IRTE (interrupt-
remapping table entry) indexed by the low 16 bits of the interrupt index.
Workaround:
Software can use requestor-id verification to block the interrupts that would be
delivered due to this erratum. Interrupts blocked in this way produce a remapping fault
with fault reason 26H.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ63.
PCIe* Link Speed May Not Change From 5.0 GT/s to 2.5 GT/s
Problem:
If a PCI Express device changes its supported PCIe link speed from 5.0 GT/s to 2.5 GT/
s without initiating a speed change request and subsequently the L1 power
management mode is entered, further retrains initiated by software will not change
speed to 2.5 GT/s.
Implication:
Intel has not observed any PCI Express device that changes supported link speed
without actually initiating a speed change.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ64.
L1 Data Cache Errors May be Logged With Level Set to 1 Instead of 0
Problem:
When an L1 Data Cache error is logged in IA32_MCi_STATUS[15:0], which is the MCA
Error Code Field, with a cache error type of the format 0000 0001 RRRR TTLL, the LL
field may be incorrectly encoded as 01 instead of 00.
Implication:
An error in the L1 Data Cache may report the same LL value as the L2 Cache. Software
should not assume that an LL value of 01 is the L2 Cache.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.