Intel E6320 Specification Update - Page 54

Workaround: Before performing a VM entry to the shutdown state, software should check whether the "virtual NMIs" and "NMI-window exiting" VM-execution controls are both 1. If they are, software should clear "NMI-window exiting" and inject an NMI as part of VM entry. Status: For the steppings affected, see the Summary Tables of Changes. BJ112. Execution of INVVPID Outside 64-Bit Mode Cannot Invalidate Translations For 64-Bit Linear Addresses Problem: Executions of the INVVPID instruction outside 64-bit mode with the INVVPID type "individual-address invalidation" ignore bits 63:32 of the linear address in the INVVPID descriptor and invalidate translations for bits 31:0 of the linear address. Implication: The INVVPID instruction may fail to invalidate translations for linear addresses that set bits in the range 63:32. Because this erratum applies only to executions outside 64-bit mode, it applies only to attempts by a 32-bit virtual-machine monitor (VMM) to invalidate translations for a 64-bit guest. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ113. VEX.L is Not Ignored with VCVT*2SI Instructions Problem: The VEX.L bit should be ignored for the VCVTSS2SI, VCVTSD2SI, VCVTTSS2SI, and VCVTTSD2SI instructions, however due to this erratum the VEX.L bit is not ignored and will cause a #UD. Implication: Unexpected #UDs will be seen when the VEX.L bit is set to 1 with VCVTSS2SI, VCVTSD2SI, VCVTTSS2SI, and VCVTTSD2SI instructions. Workaround: Software should ensure that the VEX.L bit is set to 0 for all scalar instructions. Status: For the steppings affected, see the Summary Tables of Changes. BJ114. MCI_ADDR May be Incorrect For Cache Parity Errors Problem: In cases when a WBINVD instruction evicts a line containing an address or data parity error (MCACOD of 0x124, and MSCOD of 0x10), the address of this error should be logged in the MCi_ADDR register. Due to this erratum, the logged address may be incorrect, even though MCi_Status.ADDRV (bit 63) is set. Implication: The address reported in MCi_ADDR may not be correct for cases of a parity error found during WBINVD execution. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ115. Instruction Fetches Page-Table Walks May be Made Speculatively to Uncacheable Memory Problem: Page-table walks on behalf of instruction fetches may be made speculatively to uncacheable (UC) memory. Implication: If any paging structures are located at addresses in uncacheable memory that are used for memory-mapped I/O, such I/O operations may be invoked as a result of speculative execution that would never actually occur in the executed code path. Intel has not observed this erratum with any commercially available software. Workaround: Software should avoid locating paging structures at addresses in uncacheable memory that are used for memory-mapped I/O Status: For the steppings affected, see the Summary Tables of Changes. 54 Specification Update