Intel E6320 Specification Update - Page 56
BJ118., BJ120., IA32_MC5_CTL2 is Not Cleared by a Warm Reset
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BJ118. Execution of GETSEC[SEXIT] May Cause a Debug Exception to be Lost Problem: A debug exception occurring at the same time that GETSEC[SEXIT] is executed or when an SEXIT doorbell event is serviced may be lost. Implication: Due to this erratum, there may be a loss of a debug exception when it happens concurrently with the execution of GETSEC[SEXIT]. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ119. VM Exits Due to GETSEC May Save an Incorrect Value for "Blocking by STI" in the Context of Probe-Mode Redirection Problem: The GETSEC instruction causes a VM exit when executed in VMX non-root operation. Such a VM exit should set bit 0 in the Interruptability-state field in the virtual-machine control structure (VMCS) if the STI instruction was blocking interrupts at the time GETSEC commenced execution. Due to this erratum, a VM exit executed in VMX non-root operation may erroneously clear bit 0 if redirection to probe mode occurs on the GETSEC instruction. Implication: After returning from probe mode, a virtual interrupt may be incorrectly delivered prior to GETSEC instruction. Intel has not observed this erratum with any commercially software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ120. Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior Problem: Specific source-copy blitter instructions in Intel® HD Graphics 2000 and 3000 Processor may result in unpredictable behavior when a blit source and destination overlap. Implication: Due to this erratum, the processor may exhibit unpredictable graphics controller behavior. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ121. IA32_MC5_CTL2 is Not Cleared by a Warm Reset Problem: IA32_MC5_CTL2 MSR (285H) is documented to be cleared on any reset. Due to this erratum this MSR is only cleared upon a cold reset. Implication: The algorithm documented in Software Developer's Manual, Volume 3, section titled "CMCI Initialization" or any other algorithm that counts the IA32_MC5_CTL2 MSR being cleared on reset will not function as expected after a warm reset Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ122. Problem: Performance Monitor Counters May Produce Incorrect Results When operating in hyper-threaded mode, a memory at-retirement performance monitoring event (from the list below) may be dropped or may increment an enabled counter on the physical core's other thread rather than the thread experiencing the event. The list of affected memory at-retirement events is as follows: •MEM_UOP_RETIRED.LOADS 56 Specification Update