Intel SL8K2 Specification Update - Page 53

The Execute Disable Bit Fault May Be Reported before Other Types

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Errata R R66. The Execute Disable Bit Fault May Be Reported before Other Types of Page Fault When Both Occur Problem: If the Execute Disable Bit is enabled and both the Execute Disable Bit fault and page faults occur, the Execute Disable Bit fault will be reported prior to other types of page fault being reported. Implication: No impact to properly written code since both types of faults will be generated but in the opposite order. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R67. Writes to IA32_MISC_ENABLE May Not Update Flags for Both Logical Processors Problem: On processors supporting Hyper-Threading Technology with Execute Disable Bit feature, writes to IA32_MISC_ENABLE may only update IA32_EFER.NXE for the current logical processor. Implication: Due to this erratum, the non-current logical processor may not update its IA32_EFER.NXE bit. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R68. Execute Disable Bit Set with CR4.PAE May Cause Livelock Problem: If the Execute Disable Bit of IA32_MISC_ENABLE is set along with PAE bit of CR4 (IA32_EFER.NXE & CR4.PAE), the processor may livelock. Implication: When this erratum occurs, the processor may livelock resulting in a system hang or operating system failure. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R69. Checking of Page Table Base Address May Not Match the Address Bit Width Supported by the Platform Problem: If the page table base address, included in the page map level-4 table, page-directory pointer table, page-directory table or page table, exceeds the physical address range supported by the platform (e.g. 36-bit) and it is less than the implemented address range (e.g. 40-bit), the processor does not check if the address is invalid. Implication: If software sets such invalid physical address in those tables, the processor does not generate a page fault (#PF) upon access to that virtual address, and the access results in an incorrect read or write. If BIOS provides only valid physical address ranges to the operating system, this erratum will not occur. Workaround: BIOS must provide valid physical address ranges to the operating system. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 53

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Errata
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
53
R66.
The Execute Disable Bit Fault May Be Reported before Other Types of Page
Fault When Both Occur
Problem:
If the Execute Disable Bit is enabled and both the Execute Disable Bit fault and page faults occur,
the Execute Disable Bit fault will be reported prior to other types of page fault being reported.
Implication:
No impact to properly written code since both types of faults will be generated but in the opposite
order.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R67.
Writes to IA32_MISC_ENABLE May Not Update Flags for Both Logical
Processors
Problem:
On processors supporting Hyper-Threading Technology with Execute Disable Bit feature, writes
to IA32_MISC_ENABLE may only update IA32_EFER.NXE for the current logical processor.
Implication:
Due to this erratum, the non-current logical processor may not update its IA32_EFER.NXE bit.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R68.
Execute Disable Bit Set with CR4.PAE May Cause Livelock
Problem:
If the Execute Disable Bit of IA32_MISC_ENABLE is set along with PAE bit of CR4
(IA32_EFER.NXE & CR4.PAE), the processor may livelock.
Implication:
When this erratum occurs, the processor may livelock resulting in a system hang or operating
system failure.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R69.
Checking of Page Table Base Address May Not Match the Address Bit
Width Supported by the Platform
Problem:
If the page table base address, included in the page map level-4 table, page-directory pointer
table, page-directory table or page table, exceeds the physical address range supported by the
platform (e.g. 36-bit) and it is less than the implemented address range (e.g. 40-bit), the processor
does not check if the address is invalid.
Implication:
If software sets such invalid physical address in those tables, the processor does not generate a
page fault (#PF) upon access to that virtual address, and the access results in an incorrect read or
write. If BIOS provides only valid physical address ranges to the operating system, this erratum
will not occur.
Workaround:
BIOS must provide valid physical address ranges to the operating system.
Status:
For the steppings affected, see the
Summary Tables of Changes
.