Intel SL8K2 Specification Update - Page 60

Errata R R87. FXSAVE Instruction May Result in Incorrect Data on Processors Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode of the Intel EM64T processor, the upper 32 bits of the FDP value written out to memory by the FXSAVE instruction may be incorrect. Implication: This erratum may cause incorrect data to be saved into the memory. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R88. Compatibility Mode STOS Instructions May Alter RSI Register Results on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: When a processor supporting Intel EM64T is in IA-32e mode and executes a STOS instruction in compatibility mode, it may modify the RSI register contents. Implication: When this erratum occurs, systems may encounter unexpected behavior. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R89. LDT Descriptor Which Crosses 16 bit Boundary Access Does Not Cause a #GP Fault on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: When a processor supporting Intel EM64T in IA-32e mode accesses an LDT entry (16-byte) that crosses the 0xffff limit, a #GP fault is not signaled and instead the upper 8-bytes of the entry is fetched from the wrapped around address (usually 0x0). This will cause the erroneous data to be loaded into the upper 8-bytes of the descriptor. Implication: When this erratum occurs, systems may encounter unexpected behavior. Intel has not observed this erratum with any commercially available software. Workaround: Software should prevent LDT selector accesses from crossing the 0xffff limit. Status: For the steppings affected, see the Summary Tables of Changes. R90. Upper Reserved Bits are Incorrectly Checked While Loading PDPTR's on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA32 & IA-32e mode of the Intel® processor, upper reserved bits are incorrectly checked while loading PDPTR's, allowing software to set the reserved bits. Implication: Operating system software is able to set the reserved bits which may result in an unexpected system behavior. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 60 Intel® Pentium® 4 Processor on 90 nm Process Specification Update