Intel SL8K2 Specification Update - Page 66

Attempting to Use an LDT Entry when the LDTR Has Been Loaded with an

Get Intel SL8K2 - Pentium 4 3.20EGHz 800MHz 1MB Socket 478 CPU PDF manuals and user guides
UPC - 683728107215
View all Intel SL8K2 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 66 highlights

Errata R R105. VM Entry/Exit Writes to LSTAR/SYSCALL_FLAG MSR's May Cause Incorrect Data to be Written to Bits [63:32] Problem: Incorrect MSR data in bits [63:32] may be observed in the following two cases; 1. When ECX contains 0xC0000084 and a VM entry/exit writes the IA32_CR_LSTAR MSR (MSR Address 0xC0000082) bits [63:32] of the data may be zeroed. 2. When ECX does not contain 0xC0000084 and a VM entry/exit writes the IA32_CR_SYSCALL_FLAG_MASK MSR (MSR Address 0xC0000084) bits [63:32] of the data may not be zeroed. Implication: Bits [63:32] of the affected MSRs may contain the wrong data after a VM exit/entry which loads the affected MSR. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R106. Machine Check Architecture Multiple Data Parity Errors May be Reported Problem: When the processor detects a Front Side Bus (FSB) data parity error and the core is being clocked at a ratio 12:1 or 13:1 with respect to the FSB clock, it may report multiple data parity errors. When this situation occurs, there could be multiple assertions of MCERR# until the processor receives FSB data without a parity error or a system bus reset occurs. Implication: Multiple (extraneous) data parity errors may be reported in the system. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R107. Attempting to Use an LDT Entry when the LDTR Has Been Loaded with an Unusable Segment May Cause Unexpected Memory Accesses Problem: In a system supporting Intel® EM64T and Intel® Virtualization Technology when the following occur, • The LDTR is loaded during VM entry with the segment unusable bit set for the LDTR in the VMCS (Virtual-Machine Control Structure) • The segment limit is non-zero • The granularity bit is set. References to a segment located in the LDT in 64-bit mode at any time later may cause the processor to exhibit unexpected behavior. Implication: This erratum may cause unexpected memory accesses. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 66 Intel® Pentium® 4 Processor on 90 nm Process Specification Update

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
Errata
R
66
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
R105.
VM Entry/Exit Writes to LSTAR/SYSCALL_FLAG MSR's May Cause
Incorrect Data to be Written to Bits [63:32]
Problem:
Incorrect MSR data in bits [63:32] may be observed in the following two cases;
1. When ECX contains 0xC0000084 and a VM entry/exit writes the IA32_CR_LSTAR MSR
(MSR Address 0xC0000082) bits [63:32] of the data may be zeroed.
2. When ECX does not contain 0xC0000084 and a VM entry/exit writes the
IA32_CR_SYSCALL_FLAG_MASK MSR (MSR Address 0xC0000084) bits [63:32] of the data
may not be zeroed.
Implication:
Bits [63:32] of the affected MSRs may contain the wrong data after a VM exit/entry which loads
the affected MSR.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.
R106.
Machine Check Architecture Multiple Data Parity Errors May be Reported
Problem:
When the processor detects a Front Side Bus (FSB) data parity error and the core is being clocked
at a ratio 12:1 or 13:1 with respect to the FSB clock, it may report multiple data parity errors.
When this situation occurs, there could be multiple assertions of MCERR# until the processor
receives FSB data without a parity error or a system bus reset occurs.
Implication:
Multiple (extraneous) data parity errors may be reported in the system.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
R107.
Attempting to Use an LDT Entry when the LDTR Has Been Loaded with an
Unusable Segment May Cause Unexpected Memory Accesses
Problem:
In a system supporting Intel
®
EM64T and Intel
®
Virtualization Technology when the following
occur,
•
The LDTR is loaded during VM entry with the segment unusable bit set for the LDTR in the
VMCS (Virtual-Machine Control Structure)
•
The segment limit is non-zero
•
The granularity bit is set.
References to a segment located in the LDT in 64-bit mode at any time later may cause the
processor to exhibit unexpected behavior.
Implication:
This erratum may cause unexpected memory accesses.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.