Intel SL8K2 Specification Update - Page 63

Errata R R97. The Processor May Issue Multiple Code Fetches to the Same Cache Line for Systems with Slow Memory Problem: Systems with long latencies on returning code fetch data from memory e.g. BIOS ROM, may cause the processor to issue multiple fetches to the same cache line, once per each instruction executed. Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a result of this erratum, in a commercially available system. Workaround: It is possible for the BIOS to contain a workaround for this erratum for some steppings of the processor. Status: For the steppings affected, see the Summary Tables of Changes. R98. Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service register and mask all interrupts at the same or lower priority. Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector was programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts that may occur. The ISR associated with the spurious vector does not generate an EOI, therefore the spurious vector should not be used when writing the LVT. Status: For the steppings affected, see the Summary Tables of Changes. R99. Access to an Unsupported Address Range in Uniprocessor (UP) or Dualprocessor (DP) Systems Supporting Intel® Virtualization Technology May Not Trigger Appropriate Actions Problem: When using processors supporting Intel® Virtualization Technology and configured as dual- or single-processor-capable (i.e. not multiprocessor-capable), the processor should perform address checks using a maximum physical address width of 36. Instead, these processors will perform address checks using a maximum physical address width of 40. Implication: Due to this erratum, actions which are normally taken upon detection of an unsupported address may not occur. Software which does not attempt to access unsupported addresses will not experience this erratum. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 63