Intel SL8K2 Specification Update - Page 67

The Execution of a VMPTRLD Instruction May Cause an Unexpected

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Errata R R108. The Execution of a VMPTRLD Instruction May Cause an Unexpected Memory Access Problem: In a system supporting Intel® Virtualization Technology, executing VMPTRLD may cause a memory access to an address not referenced by the memory operand. Implication: This erratum may cause unpredictable system behavior including system hang. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R109. The Execution of VMPTRLD or VMREAD May Cause an Unexpected Memory Access Problem: On processors supporting Intel® Virtualization Technology, executing a VMPTRLD or a VMREAD instruction outside of VMX mode may result in a load to an unexpected address. Implication: This erratum may cause a load to an unexpected memory address. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R110. IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte boundary before pushing the stack frame. Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment checks are disabled at the start of the IRET. This erratum can only be observed with a software generated stack frame. Workaround: Software should not generate misaligned stack frames for use with IRET. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 67

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Errata
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
67
R108.
The Execution of a VMPTRLD Instruction May Cause an Unexpected
Memory Access
Problem:
In a system supporting Intel
®
Virtualization Technology, executing VMPTRLD may cause a
memory access to an address not referenced by the memory operand.
Implication:
This erratum may cause unpredictable system behavior including system hang.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.
R109.
The Execution of VMPTRLD or VMREAD May Cause an Unexpected
Memory Access
Problem:
On processors supporting Intel
®
Virtualization Technology, executing a VMPTRLD or a
VMREAD instruction outside of VMX mode may result in a load to an unexpected address.
Implication:
This erratum may cause a load to an unexpected memory address.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.
R110.
IRET under Certain Conditions May Cause an Unexpected Alignment Check
Exception
Problem:
In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET
instruction even though alignment checks were disabled at the start of the IRET.
This can only
occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2
are not affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set,
and the interrupt handler's stack is misaligned.
In IA-32e mode, RSP is aligned to a 16-byte
boundary before pushing the stack frame.
Implication:
In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment
checks are disabled at the start of the IRET.
This erratum can only be observed with a software
generated stack frame.
Workaround:
Software should not generate misaligned stack frames for use with IRET.
Status:
For the steppings affected, see the
Summary Tables of Changes.