Sony MDS-JE470 Service Manual - Page 53

IC151 CXD2662R Digital Signal Processor, Digital Servo Signal Processor BD BOARD, Desription, Pin No.

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MDS-JE470 • IC151 CXD2662R Digital Signal Processor, Digital Servo Signal Processor (BD BOARD) Pin No. Pin Name I/O Desription 1 MNT0 (FOK) O Not used (open) 2 MNT1 (SHCK) O Track jump detection signal output to the system control 3 MNT2 (XBUSY) O In the state of executire command signal output 4 MNT3 (SLOC) O Not used (open) 5 SWDT I Writing data signal input from the system control 6 SCLK I (S) Serial clock signal input from the system control 7 XLAT I (S) Serial latch signal input from the system control 8 SRDT O (3) Reading data signal output to the system control 9 SENS O (3) Internal status (SENSE) output to the system control 10 XRST I (S) Reset signal input from the system control "L": Reset 11 SQSY Subcode Q sync (SCOR) output to the system control O "L" is output every 13.3 msec. Almost all, "H" is output 12 DQSY Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system O control 13 RECP I Laser power switching input from the system control "H": Recording, "L": Playback 14 XINT O Interrupt status output to the system control 15 TX O Recording data output enable input from the system control 16 OSCI I System clock input (512Fs=22.5792 MHz) 17 OSCO O System clock output (512Fs=22.5792 MHz) (Not used) 18 XTSL I System clock frequency setting "L": 45.1584 MHz, "H": 22.5792 MHz (Fixed at "H") 19 DIN0 I Digital audio input (Optical input) 20 DIN1 I Digital audio input (Optical input) (Not used) 21 DOUT O Digital audio output (Optical output) (Not used) 22 DADTI I Serial data input 23 LRCKI I LR clock input "H" : Lch, "L" : R ch 24 XBCKI I Serial data clock input 25 ADDT I Data input from the A/D converter 26 DADT O Data output to the D/A converter 27 LRCK O LR clock output for the A/D and D/A converter (44.1 kHz) 28 XBCK O Bit clock output to the A/D and D/A converter (2.8224 MHz) 29 FS256 O 11.2896 MHz clock output (Not used) 30 DVDD I +3V power supply (Digital) 31 - 34 A03 to A00 O DRAM address output 35 A10 O DRAM address output (Not used) 36 - 40 A04 to A08 O DRAM address output 41 A11 O DRAM address output (Not used) 42 DVSS - Ground (Digital) 43 XOE O Output enable output for DRAM 44 XCAS O CAS signal output for DRAM 45 A09 O Address output for DRAM 46 XRAS O RAS signal output for DRAM 47 XWE O Write enable signal output for DRAM * I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O 53

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53
MDS-JE470
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
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4
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IC151 CXD2662R Digital Signal Processor, Digital Servo Signal Processor (BD BOARD)
Desription
Pin No.
Pin Name
I/O
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
O
I
O
I
I
I
O
I
I
I
I
O
O
O
O
I
O
O
O
O
—
O
O
O
O
O
Not used (open)
Track jump detection signal output to the system control
In the state of executire command signal output
Not used (open)
Writing data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system
control
Laser power switching input from the system control
“H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
System clock input (512Fs=22.5792 MHz)
System clock output (512Fs=22.5792 MHz) (Not used)
System clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)
Digital audio input (Optical input)
Digital audio input (Optical input) (Not used)
Digital audio output (Optical output) (Not used)
Serial data input
LR clock input
“H” : Lch, “L” : R ch
Serial data clock input
Data input from the A/D converter
Data output to the D/A converter
LR clock output for the A/D and D/A converter (44.1 kHz)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM
address output
DRAM
address output (Not used)
DRAM
address output
DRAM
address output (Not used)
Ground (Digital)
Output enable output for DRAM
CAS signal output for DRAM
Address output for DRAM
RAS signal output for DRAM
Write enable signal output for DRAM
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O