Toshiba SD-M1212 Product Specification - Page 20

6.2.2. Timing of Host Interface (PIO) Figure 8 shows the Host Interface Timings. Address valid*1 t2 t1 DIOR-/DIOWWrite data valid*2 Read data valid*2 t0 t3 IOCS16IORDY t7 tA t5 tB tRD t9 t2i t8 t4 t6Z t6 *1:Device Address consists of signals CS0-, CS1-, and DA2-0 *2:Data consists of DD0-15 (16-bit) or DD0-7 (8-bit) PIO timing parameters min(ns) max(ns) t0 Cycle time t1 Address valid to DIOR-/DIOW-setup t2 DIOR-/DIOW- pulse wide t2i DIOR-/DIOW- recovery time t3 DIOW- data setup t4 DIOW- data hold t5 DIOR- data setup t6 DIOR- data hold t6Z DIOR- data tristate t7 Addr valid to IOCS16- assertion t8 Addr valid to IOCS16- negation t9 DIOR-/DIOW- to address valid hold tRD Read Data Valid to IORDY active tA IORDY setup time tB IORDY pulse wide Min Time (ns) 120 25 70 25 20 10 20 5 10 0 Max Time (ns) 30 30 30 35 1250 Figure 8 Host Interface Timing 14/28 SD-M1212 Rev.1.0