Toshiba SD-M1212 Product Specification - Page 22

6.2.4.Timing of Host Interface (DMA Multi) Figure 10 shows the Host Interface DMA multi word Timings DMARQ DMACK-*1 DIOR-/DIOW-*1 Read DD0-1 Write DD0-1 t0 tD tK tI tE tF tG tH tL tJ tZ *1: In all timing diagrams, the low line indicator negated, and the upper line indicators asserted. Multi word DMA timing parameters min(ns) max(ns) t0 Cycle time tC DMACK to DMREQ delay tD DIOR-/DIOW- 16-bit tE DIOR- data access tF DIOR- data hold tZ DMACK- to tristate tG DIOR/DIOW- data setup tH DIOW- data hold tI DMACK to DIOR-/DIOW- setup tJ DIOR-/DIOW- to DMACK hold tKr DIOR- negated pulse width tKw DIOW- negated pulse width tLr DIOR- to DMREQ delay tLw DIOR- to DMREQ delay Min time (ns) 120 70 5 20 10 0 5 25 25 Figure 10 Host Interface Timing (DMA Multi) Max time (ns) ----- 25 35 35 16/28 SD-M1212 Rev.1.0