Toshiba SD-M1212 Product Specification - Page 23

6.2.5.Timing of Host Interface (Ultra DMA) Figure 11 shows the Host Interface Ultra DMA Timings STROBE DIOR/IORDY DD (15:0) Send tCYC t2CYC tCYC t2CYC t DVH tDVS t DVH tDVS tDVH STROBE IORDY/DIOR t DH DD (15:0) Recive t DS t DH t DS tDH Note: DD (15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow signal to be considered stable at the host unit some time after they are drive by the device. NAME tCYC t2CYC tDS tDH tDVS tDVH MODE 0 MIN MAX 114 235 15 5 70 6 MODE 1 MIN MAX 75 156 10 5 48 6 MODE 2 MIN 55 MAX 117 7 5 34 6 COMMENT Cycle time (from STROBE edge to STROBE edge) Two cycle time (from risingedge to next rising edge of from falling edge to next falling edge of STROBE) Data setup time (at recipient) Data hold time (at recipient) Data valid setup time at sender (time form data bus being valid until STROBE edge) Data valid hold time at sender (time form STROBE edge until data may go invalid) Figure 11 Host inter face timing (Ultra DMA) 17/28 SD-M1212 Rev.1.0