Toshiba SD-M1212 Product Specification - Page 21

6.2.3.Timing of Host Interface (DMA Single) Figure 9 shows the Host Interface DMA single word Timings DMARQ DMACK-*1 DIOR-/DIOW-*1 Read DD0-15 Write DD0-15 t0 tC tI tJ tD tE tS tF tG tH *1: In all timing diagrams, the low line indicator negated, and the upper line indicators asserted. Single word DMA timing parameters min(ns) max(ns) Min time (ns) t0 Cycle time 240 tC DMACK to DMREQ delay tD DIOR-/DIOW- 16-bit 120 tE DIOR- data access tF DIOR- data hold 5 tG DIOW- data setup 35 tH DIOW- data hold 20 tI DMACK to DIOR-/DIOW- setup 0 tJ DIOR-/DIOW- to DMACK hold 0 tS DIOR- setup tD - tE Figure 9 Host Interface Timing (DMA Single) Max time (ns) 80 60 15/28 SD-M1212 Rev.1.0