Asus A7V8X-MX SE A7V8X-MX SE User's Manual - Page 46

DRAM Command Rate [2T Command]

Page 46 highlights

DRAM Burst Lenght [4] Configuration options: [4] [8] DRAM Command Rate [2T Command] Configuration options: [2T Command] [1T Command] Write Recovery Time [3T] Configuration options: [3T] [2T] CPU & PCI Bus Control CPU & PCI Bus Control PCI1 Master 0 WS Write PCI2 Master 0 WS Write PCI1 Post Write PCI2 Post Write VLink 8X Support PCI Delay Transaction [Enabled] [Enabled] [Enabled] [Enabled] [Enabled] [Enabled] Select Menu Item Specific Help F1 : Help ↑↓ : Select Item -/+ : Change Value F5 : Setup Defaults ESC : Exit →← : Select Menu Enter : Select Sub-menu F10 : Save and Exit PCI1 Master 0 WS Write [Enabled] PCI2 Master 0 WS Write [Enabled] Configuration options: [Enabled] [Disabled] PCI1 Post Write [Enabled] PCI2 Post Write [Enabled] Configuration options: [Enabled] [Disabled] VLink 8X Support [Enabled] This option enables or disables the VLink 8X feature of the motherboard. The VLink 8X technology allows high bandwidth connection between the North bridge and South bridge chipsets. Configuration options: [Enabled] [Disabled] PCI Delay Transaction [Enabled] When set to [Enabled], this feature frees the PCI bus when the CPU is accessing 8-bit ISA cards. This process consumes 50-60 PCI clocks without PCI delayed transaction. Set this field to [Disabled] when using ISA cards that are not PCI 2.2 compliant. Configuration options: [Enabled] [Disabled] 2-16 Chapter 2: BIOS information

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2-16
Chapter 2: BIOS information
CPU & PCI Bus Control
PCI1 Master 0 WS Write [Enabled]
PCI2 Master 0 WS Write [Enabled]
Configuration options:
[Enabled] [Disabled]
PCI1 Post Write [Enabled]
PCI2 Post Write [Enabled]
Configuration options:
[Enabled] [Disabled]
VLink 8X Support [Enabled]
This option enables or disables the VLink 8X feature of the motherboard. The
VLink 8X technology allows high bandwidth connection between the North bridge
and South bridge chipsets. Configuration options: [Enabled] [Disabled]
PCI Delay Transaction [Enabled]
When set to [Enabled], this feature frees the PCI bus when the CPU is accessing
8-bit ISA cards. This process consumes 50-60 PCI clocks without PCI delayed
transaction. Set this field to [Disabled] when using ISA cards that are not PCI 2.2
compliant. Configuration options:
[Enabled] [Disabled]
DRAM Burst Lenght [4]
Configuration options: [4] [8]
DRAM Command Rate [2T Command]
Configuration options: [2T Command] [1T Command]
Write Recovery Time [3T]
Configuration options: [3T] [2T]
PCI1 Master 0 WS Write
[Enabled]
PCI2 Master 0 WS Write
[Enabled]
PCI1 Post Write
[Enabled]
PCI2 Post Write
[Enabled]
VLink 8X Support
[Enabled]
PCI Delay Transaction
[Enabled]
CPU & PCI Bus Control
F1
: Help
↑↓
: Select Item
-/+
: Change Value
F5
: Setup Defaults
ESC : Exit
→←
: Select Menu
Enter : Select Sub-menu
F10 : Save and Exit
Select Menu
Item Specific Help