Asus ROG MAXIMUS Z790 FORMULA ROG Z790 Series BIOS Manual English - Page 30

MC0 Dimm0 / MC0 Dimm1 / MC1 Dimm0 / MC1 Dimm1, Read Equalization RxEq Stop Sign

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Page 30 highlights

Ctl0 dqodtvrefdn Configuration options: [Auto] [0] - [255] Ctl1 cmdvrefup Configuration options: [Auto] [0] - [255] Ctl1 ctlvrefup Configuration options: [Auto] [0] - [255] Ctl1 clkvrefup Configuration options: [Auto] [0] - [255] Ctl1 ckecsvrefup Configuration options: [Auto] [0] - [255] Ctl2 cmdvrefdn Configuration options: [Auto] [0] - [255] Ctl2 ctlvrefdn Configuration options: [Auto] [0] - [255] Ctl2 clkvrefdn Configuration options: [Auto] [0] - [255] Equalization page Read Equalization RxEq Start Sign Configuration options: [-] [+] Read Equalization RxEq Start Configuration options: [Auto] [0] - [15] Read Equalization RxEq Stop Sign Configuration options: [-] [+] Read Equalization RxEq Stop Configuration options: [Auto] [0] - [15] Tc Odt Control ODT_READ_DURATION Configuration options: [Auto] [0] - [15] ODT_READ_DELAY Configuration options: [Auto] [0] - [15] ODT_WRITE_DURATION Configuration options: [Auto] [0] - [15] ODT_WRITE_DELAY Configuration options: [Auto] [0] - [15] MC0 Dimm0 / MC0 Dimm1 / MC1 Dimm0 / MC1 Dimm1 DQ RTT WR Configuration options: [Auto] [0 DRAM Clock] [34 DRAM Clock] [40 DRAM Clock] [48 DRAM Clock] [60 DRAM Clock] [80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock] DQ RTT NOM RD Configuration options: [Auto] [0 DRAM Clock] [34 DRAM Clock] [40 DRAM Clock] [48 DRAM Clock] [60 DRAM Clock] [80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock] DQ RTT NOM WR Configuration options: [Auto] [0 DRAM Clock] [34 DRAM Clock] [40 DRAM Clock] [48 DRAM Clock] [60 DRAM Clock] [80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock] 30 ROG Z790 Series (Intel® 14th) BIOS Manual

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30
ROG Z790 Series (Intel
®
14
th
) BIOS Manual
Ctl0 dqodtvrefdn
Configuration options: [Auto] [0] - [255]
Ctl1 cmdvrefup
Configuration options: [Auto] [0] - [255]
Ctl1 ctlvrefup
Configuration options: [Auto] [0] - [255]
Ctl1 clkvrefup
Configuration options: [Auto] [0] - [255]
Ctl1 ckecsvrefup
Configuration options: [Auto] [0] - [255]
Ctl2 cmdvrefdn
Configuration options: [Auto] [0] - [255]
Ctl2 ctlvrefdn
Configuration options: [Auto] [0] - [255]
Ctl2 clkvrefdn
Configuration options: [Auto] [0] - [255]
Equalization page
Read Equalization RxEq Start Sign
Configuration options: [-] [+]
Read Equalization RxEq Start
Configuration options: [Auto] [0] - [15]
Read Equalization RxEq Stop Sign
Configuration options: [-] [+]
Read Equalization RxEq Stop
Configuration options: [Auto] [0] - [15]
Tc Odt Control
ODT_READ_DURATION
Configuration options: [Auto] [0] - [15]
ODT_READ_DELAY
Configuration options: [Auto] [0] - [15]
ODT_WRITE_DURATION
Configuration options: [Auto] [0] - [15]
ODT_WRITE_DELAY
Configuration options: [Auto] [0] - [15]
MC0 Dimm0 / MC0 Dimm1 / MC1 Dimm0 / MC1 Dimm1
DQ RTT WR
Configuration options: [Auto] [0 DRAM Clock] [34 DRAM Clock] [40 DRAM Clock] [48
DRAM Clock] [60 DRAM Clock] [80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock]
DQ RTT NOM RD
Configuration options: [Auto] [0 DRAM Clock] [34 DRAM Clock] [40 DRAM Clock] [48
DRAM Clock] [60 DRAM Clock] [80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock]
DQ RTT NOM WR
Configuration options: [Auto] [0 DRAM Clock] [34 DRAM Clock] [40 DRAM Clock] [48
DRAM Clock] [60 DRAM Clock] [80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock]