IBM 8687 Installation Guide - Page 33

1.6 IBM XceL4 Server Accelerator Cache Integrated into each SMP Expansion Module is 32 MB of high-speed Level 4 cache (see Figure 1-10). This XceL4 Server Accelerator Cache provides the necessary extra level of cache to alleviate the bottlenecks caused by memory latency across the scalability port. Cache memory is two-way interleaved 200 MHz DDR memory and is faster than standard memory because it is directly connected to the memory controller and does not have additional latency associated with the large fan-out necessary to support the 16 DIMM slots. Initial tests have shown the XceL4 cache has improved overall system performance up to 20% on various applications. 1.7 System memory The Xeon MP models of the x440 have 2 GB or 4 GB of RAM standard, implemented as four PC133 ECC SDRAM DIMMs (four 512 MB or four 1 GB DIMMs). There are 16 DIMM sockets (two ports of eight) in each of the two SMP Expansion Modules for a total of 32 sockets. Using 2 GB DIMMs, this means that each x440 can have up to 64 GB RAM. See 3.1.2, "Memory" on page 65 for further discussion of how memory is implemented in the x440 and what you should consider before an x440 installation. There are a number of advanced features implemented in the x440 memory subsystem, collectively known as Active Memory: Memory ProteXion Memory ProteXion, also known as "redundant bit steering", is the technology behind using redundant bits in a data packet to provide backup in the event of a DIMM failure. Currently, other industry-standard servers use 8 bits of the 72-bit data packets for ECC functions and the remaining 64 bits for data. However, because the x440 uses four-way interleaved memory, it needs only 6 bits to perform the same ECC functions, thus leaving 2 bits free (Figure 1-11 on page 20). Chapter 1. Technical description 19