Intel DN2800MT Technical Product Specification for Intel Desktop Board DN2800M - Page 62

Debug Header, 2.3.7, Custom Solutions Header - specs

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Intel Desktop Board DN2800MT Technical Product Specification 2.2.3.6 Debug Header During the POST, the BIOS generates diagnostic progress codes (POST codes) to I/O port 80h. If the POST fails, execution stops and the last POST code generated is left at port 80h. This code is useful for determining the point where an error occurred. Displaying the POST codes requires a POST card that can interface with the Debug header. The POST card can decode the port and display the contents on a medium such as a seven-segment display. Table 37. Debug Header Pin 1 2 3 4 5 6 7 8 9 10 11 Signal Name VCC3 VCC3 PLTRST# LPC_CLK LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LFRAME/FWH4# GND GND 2.2.3.7 Custom Solutions Header The Customs Solution header is provided to aid customers in developing unique applications. • WDTO#: indicates when the Watchdog Timer in the Super I/O device has expired. This is a general purpose implementation that can be wired to external systems (i.e., industrial control, etc.) or to the reset pin on the board (if the intended use is to reset the board). Intel can provide sample code for customers who write their own applications that require Watchdog Timer support. • SMB_CLK and SMB_DATA: SMBus interface, reserved for Intel use. General SMBus information can be found on the platform EDS and at http://smbus.org/specs/. • 3.3 V Standby: can be used to monitor the presence of 3.3 V standby power (functions in the same manner as the 3.3 V standby power LED). • PWRBT#: power button signal (functions in the same manner as the power button pin on the front panel header). • HDMI Consumer Electronics Control (CEC): standard communication signal from the HDMI connector (http://www.hdmi.org/) - the signal is exposed through the Custom Solutions header for third party solutions to monitor/control CEC activity between multiple HDMI devices. 62

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Intel Desktop Board DN2800MT Technical Product Specification
62
2.2.3.6
Debug Header
During the POST, the BIOS generates diagnostic progress codes (POST codes) to I/O
port 80h.
If the POST fails, execution stops and the last POST code generated is left at
port 80h.
This code is useful for determining the point where an error occurred.
Displaying the POST codes requires a POST card that can interface with the Debug
header.
The POST card can decode the port and display the contents on a medium
such as a seven-segment display.
Table 37.
Debug Header
Pin
Signal Name
1
VCC3
2
VCC3
3
PLTRST#
4
LPC_CLK
5
LAD0/FWH0
6
LAD1/FWH1
7
LAD2/FWH2
8
LAD3/FWH3
9
LFRAME/FWH4#
10
GND
11
GND
2.2.3.7
Custom Solutions Header
The Customs Solution header is provided to aid customers in developing unique
applications.
•
WDTO#: indicates when the Watchdog Timer in the Super I/O device has expired.
This is a general purpose implementation that can be wired to external systems
(i.e., industrial control, etc.) or to the reset pin on the board (if the intended use is
to reset the board).
Intel can provide sample code for customers who write their
own applications that require Watchdog Timer support.
•
SMB_CLK and SMB_DATA: SMBus interface, reserved for Intel use.
General SMBus
information can be found on the platform EDS and at http://smbus.org/specs/.
•
3.3 V Standby: can be used to monitor the presence of 3.3 V standby power
(functions in the same manner as the 3.3 V standby power LED).
•
PWRBT#: power button signal (functions in the same manner as the power button
pin on the front panel header).
•
HDMI Consumer Electronics Control (CEC): standard communication signal from
the HDMI connector (http://www.hdmi.org/) - the signal is exposed through the
Custom Solutions header for third party solutions to monitor/control CEC activity
between multiple HDMI devices.