MSI MS-7222-020 User Guide - Page 47

REF to ACT / REF to REF Trfc

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Page 47 highlights

MS-7222 Micro-ATX Mainboard DRAM Timing Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect) EEPROM on the DRAM module. Setting to [Auto By SPD] enables the following fields automatically to be determined by BIOS based on the configurations on the SPD. Selecting [Manual] allows users to configure these fields manually. SDRAM CAS Latency [DDR/DDR2] This controls the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. Settings: [1.5/ 2], [2/ 3], [2.5/ 4], [3/ 5] increases the system performance the most while [3/ 5] provides the most stable performance. Bank Interleave This field selects 2-bank, 4-bank or 8-bank interleave for the installed SDRAM. Disable the function if 16MB SDRAM is installed. Precharge to Active (Trp) This setting controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. Setting options: [2T], [3T], [4T], [5T]. Active to Precharge (Tras) This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. Available settings: [05T]~ [20T]. Active to CMD (Trcd) When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. Settings: [2T], [3T], [4T], [5T]. REF to ACT / REF to REF (Trfc) This setting determines the time RFC takes to read from and write to a memory cell. Setting options: [08T]~ [71T]. ACT(0) to ACT(1) (TRRD) This field specifies The Row to Row delay of different banks.Setting options: [2T], [3T], [4T], [5T]. Read to Precharge (Trtp) This item controls the internal Read to Precharge command delay. Setting options: [2T], [3T]. 3-10

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MS-7222 Micro-ATX Mainboard
DRAM Timing
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to [Auto By SPD] enables the following
fields automatically to be determined by BIOS based on the configurations on the
SPD.
Selecting [Manual] allows users to configure these fields manually.
SDRAM CAS Latency [DDR/DDR2]
This controls the timing delay (in clock cycles) before SDRAM starts a read com-
mand after receiving it. Settings: [1.5/ 2], [2/ 3], [2.5/ 4], [3/ 5] increases the system
performance the most while [3/ 5] provides the most stable performance.
Bank Interleave
This field selects 2-bank, 4-bank or 8-bank interleave for the installed SDRAM.
Disable the function if 16MB SDRAM is installed.
Precharge to Active (Trp)
This setting controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to accumulate its
charge before DRAM refresh, refresh may be incomplete and DRAM may fail to
retain data. This item applies only when synchronous DRAM is installed in the
system. Setting options: [2T], [3T], [4T], [5T].
Active to Precharge (Tras)
This item controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to accumulate its
charge before DRAM refresh, refresh may be incomplete and DRAM may fail to
retain data. This item applies only when synchronous DRAM is installed in the
system. Available settings: [05T]~ [20T].
Active to CMD (Trcd)
When DRAM is refreshed, both rows and columns are addressed separately.
This setup item allows you to determine the timing of the transition from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance. Settings: [2T], [3T], [4T], [5T].
REF to ACT / REF to REF (Trfc)
This setting determines the time RFC takes to read from and write to a memory cell.
Setting options: [08T]~ [71T].
ACT(0) to ACT(1) (TRRD)
This field specifies The Row to Row delay of different banks.Setting options: [2T],
[3T], [4T], [5T].
Read to Precharge (Trtp)
This item controls the internal Read to Precharge command delay. Setting options:
[2T], [3T].