Sony STR-DB830 Service Manual - Page 33

Sony STR-DB830 - Fm Stereo/fm-am Receiver Manual

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Pin No. 31 32 33 34 Pin Name RIN- RIN+ VREFL VCOM 35 VREFH 36 A. 5V 37 A. GND 38 XTI 39 MCLKI 40 S/P 41 CS 42 CCLK 43 CDTI 44 CDTO I/O Description I Rch analog negative input pin I Rch analog positive input pin I Negative voltage reference input pin, AVSS (Connected to ground) Common voltage output pin, AVDD/2 O Large external capacitor is used to reduce power-supply noise I Positive voltage reference input pin, AVDD - Analog power supply pin - Analog ground pin I X'tal input pin (Not used) I External master clock input pin if XTS = "L" Parallel/serial select pin I "L": serial control mode, "H": parallel control mode (Connected to ground) I Chip select pin in serial mode I Control data clock pin in serial mode I Control data input in serial mode O Control data output pin in serial mode If pins TEST, ICKS0, ICKS1, PD, S/P, DFS, DEM0, DEM1, CAD0, CAD1, S/M, MCLK, SDOS are not driven, then TEST, ICKS0, ICKS1, CAD0, CAD1, must be tied to either AVSS or AVDD. PD, S/P, DFS, DEM0, DEM1, S/M, MCLK, SDOS must be tied to either DVSS or DVDD. - 55 -

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— 55 —
Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O
I
I
I
O
I
—
—
I
I
I
I
I
I
O
Description
Rch analog negative input pin
Rch analog positive input pin
Negative voltage reference input pin, AVSS (Connected to ground)
Common voltage output pin,
AVDD/2
Large external capacitor is used to reduce power-supply noise
Positive voltage reference input pin, AVDD
Analog power supply pin
Analog ground pin
X’tal input pin (Not used)
External master clock input pin if XTS = “L”
Parallel/serial select pin
“L”: serial control mode, “H”: parallel control mode (Connected to ground)
Chip select pin in serial mode
Control data clock pin in serial mode
Control data input in serial mode
Control data output pin in serial mode
Pin Name
RIN–
RIN+
VREFL
VCOM
VREFH
A. 5V
A. GND
XTI
MCLKI
S/P
CS
CCLK
CDTI
CDTO
If pins TEST, ICKS0, ICKS1, PD, S/P, DFS, DEM0, DEM1, CAD0, CAD1, S/M, MCLK, SDOS are not driven, then TEST, ICKS0, ICKS1, CAD0, CAD1,
must be tied to either AVSS or AVDD. PD, S/P, DFS, DEM0, DEM1, S/M, MCLK, SDOS must be tied to either DVSS or DVDD.