Asus TS500-E4 PX4 TS500-E4 - Page 115

Echo TPR [Disabled] Configuration options: [Disabled] [Enabled] Discrete MTRR Allocation [Disabled] Configuration options: [Disabled] [Enabled] Intel EIST support [Enabled] Enables or disables EIST support. Configuration options: [Disabled] [Enabled] No Execute Mode Mem Protection [Enabled] Configuration options: [Disabled] [Enabled] Adjacent Cache Line Prefetch [Enabled] Configuration options: [Disabled] [Enabled] Set Max Ext CPUID = 3 [Disabled] Enable this item to boot legacy operating systems that cannot support CPUs with extended CPUID functions. Configuration options: [Disabled] [Enabled] 5.4.2 Chipset Configuration This menu shows the chipset configuration settings. Select an item then press to display a pop-up menu with the configuration options. Advanced PhoenixBIOS Setup Utility Chipset Configuration Crystal Beach Configure Enable SERR Signal Condition Demand Scrub Enable Patrol Scrub Enable 4GB PCI Hole Granularity Memory Branch Mode Branch 0 Rank Interleave Branch 0 Rank Sparing Enhanced x8 Detection Force ITK Config Clocking FBDIMM(s) Thermal Throttling Open Loop Type Environment Temperature Item Specific Help [Enabled] [Single Bit] [Enabled] [Enabled] [256 MB] [Interleave] [4:1] [Disabled] [Enabled] [Disabled] Enable Configuration/ Memory mapped accesses to the Crystal Beach Configuration space located in Device 8, Fn 0, and Fn 1. [Open Loop] [Best Performan] [025 OC] F1 Help ESC Exit ↑↓ Select Item →← Select Menu -/+ Change Values F9 Setup Defaults Enter Select Sub-Menu F10 Save and Exit Scroll down to display the following item: Temperature Rise FBDIMM(S) Air Flow [025 OC] [2.0] F1 Help ESC Exit ↑↓ Select Item →← Select Menu -/+ Change Values F9 Setup Defaults Enter Select Sub-Menu F10 Save and Exit ASUS TS500-E4 5-21