Fujitsu MHN2100AT Manual/User Guide - Page 163
READ/WRITE DMA QUEUED commands supported, Bit 15-9: Reserved
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5.3 Host Commands Table 5.16 DEVICE CONFIGURATION IDENTIFY data structure Word 0 1 2 3-6 7 8-254 255 Value X'0001' X'0007' X'003F' X'00CF' X'0000' X'xxA5' Content Data structure revision Multiword DMA modes supported Bit 15-3: Reserved Bit 2: 1 = Multiword DMA mode 2 and below are supported Bit 1: 1 = Multiword DMA mode 1 and below are supported Bit 0: 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported Bit 15-6: Reserved Bit 5: 1 = Ultra DMA mode 5 and below are supported Bit 4: 1 = Ultra DMA mode 4 and below are supported Bit 3: 1 = Ultra DMA mode 3 and below are supported Bit 2: 1 = Ultra DMA mode 2 and below are supported Bit 1: 1 = Ultra DMA mode 1 and below are supported Bit 0: 1 = Ultra DMA mode 0 is supported Maximum LBA address Command set/feature set supported Bit 15-9: Reserved Bit 8: 1 = 48-bit Addressing feature set supported Bit 7: 1 = Host Protected Area feature set supported Bit 6: 1 = Automatic acoustic management supported Bit 5: 1 = READ/WRITE DMA QUEUED commands supported Bit 4: 1 = Power-up in Standby feature set supported Bit 3: 1 = Security feature set supported Bit 2: 1 = SMART error log supported Bit 1: 1 = SMART self-test supported Bit 0: 1 = SMART feature set supported Reserved Integrity word. Bits 15:8 contains the data structure checksum that is the two's complement of the sum of all byte in words 0 through 254 and the byte consisting of bits 7:0 of word 255. C141-E120-02EN 5-87