Intel 945G User Manual - Page 20

Intel® 945G Express Chipset Development Kit User's Manual Development Kit Features PCI Express* Interface The ICH7 has 4x PCI Express root ports (ports 1-4), supporting the PCI Express Base Specification, Revision 1.0a. PCI Express root ports 1-4 can be statically configured as four x1 ports or ganged together to form one x4 port. Each root port supports 2.5 Gb/s bandwidth in each direction (5 Gb/s concurrent). Serial ATA (SATA) Controller The ICH7 has an integrated SATA host controller that supports independent DMA operation on four ports and supports data transfer rates of up to 3.0 Gb/s (300 MB/s). The SATA controller for this development kit contains the legacy mode using I/O space operation. The ICH7 supports the Serial ATA Specification, Revision 1.0a. The ICH7 also supports optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0. IDE Interface (Bus Master Capability and Synchronous DMA Mode) The fast IDE interface supports up to two IDE devices providing an interface for IDE hard disks and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to 16 MB/s and Ultra ATA transfers up to 100 MB/s. It does not consume any legacy DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers. The ICH7's IDE system contains a single, independent IDE signal channel that can be electrically isolated. There are integrated series resistors on the data and control lines. PCI Interface The ICH7 PCI interface provides a 33 MHz, Revision 2.3 implementation. The ICH7 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH7 requests. This allows for combinations of up to six PCI down devices and PCI slots. Low Pin Count (LPC) Interface The ICH7 implements an LPC Interface as described in the LPC 1.1 Specification. The LPC bridge function of the ICH7 resides in PCI Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional units including DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC. Serial Peripheral Interface (SPI) The ICH7 implements an SPI Interface as an alternative interface for the BIOS flash device. An SPI flash device can be used as a replacement for the firmware hub. Universal Serial Bus (USB) Controller The ICH7 contains an Enhanced Host Controller Interface (EHCI) host controller that supports USB Hi-Speed signaling. Hi-Speed USB 2.0 allows data transfers up to 480 Mb/s, which is up to 40 times faster than full-speed USB. The ICH7 also contains four Universal Host Controller Interface (UHCI) controllers that support USB full-speed and low-speed signaling. The ICH7 supports eight USB 2.0 ports. All eight ports are Hi-Speed, full-speed, and lowspeed capable. ICH7's port-routing logic determines whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller. 20 Reference #308823