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Intel D845GVFN Product Specification - Page 44

Table 20., PCI Interrupt Routing Map

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Intel Desktop Board D845GVFN Technical Product Specification Table 20. PCI Interrupt Routing Map PCI Interrupt Source Intel Extreme Graphics Controller ICH4 USB UHCI controller 1 SMBus controller ICH4 USB UHCI controller 2 AC '97 ICH4 Audio/Modem ICH4 LAN ICH4 USB UHCI controller 3 ICH4 USB 2.0 EHCI controller PCI bus connector 1 PCI bus connector 2 PCI bus connector 3 PIRQA PIRQB INTA INTA INTB INTB INTD INTC ICH4 PIRQ Signal Name PIRQC PIRQD PIRQE PIRQF INTB INTC INTA INTA INTB INTD INTC INTA INTB PIRQG INTB INTA PIRQH INTD INTC INTD NOTE In PIC mode, the ICH4 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 19 for the allocation of PIRQ lines to IRQ signals in APIC mode. 44

Section	Page
Intel® Desktop Board D845GVFN Technical Product Specification	1
Revision History / Disclaimer	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Other Common Notation	4
Contents	5
1 Product Description	9
1.1 Overview	10
1.1.1 Feature Summary	10
1.1.2 Manufacturing Options	11
1.1.3 Board Layout	12
1.2 Block Diagram	13
1.3 Online Support	14
1.4 Operating System Support	14
1.5 Design Specifications	15
1.6 Processor	18
1.7 System Memory	19
1.8 Intel® 845GV Chipset	21
1.8.1 Intel® Extreme Graphics Controller	21
1.8.2 USB	26
1.8.3 IDE Interfaces	26
1.8.4 Real-Time Clock, CMOS SRAM, and Battery	27
1.9 I/O Controller	28
1.9.1 Serial Ports	28
1.9.2 Parallel Port	28
1.9.3 Diskette Drive Controller	28
1.9.4 Keyboard and Mouse Interface	28
1.10 Audio Subsystem	29
1.10.1 Audio Connectors	29
1.10.2 Audio Subsystem Software	30
1.11 LAN Subsystem (Optional)	30
1.11.1 Intel® 82562ET Platform LAN Connect Device	30
1.11.2 RJ-45 LAN Connector with Integrated LEDs	31
1.11.3 LAN Subsystem Software	31
1.12 Hardware Management Subsystem (Optional)	31
1.12.1 Hardware Monitoring and Fan Control ASIC	31
1.12.2 Fan Monitoring	32
1.12.3 Chassis Intrusion and Detection	32
1.13 Power Management	32
1.13.1 ACPI	32
1.13.2 Hardware Support	35
2 Technical Reference	39
2.1 Introduction	39
2.2 Memory Map	39
2.3 Fixed I/O Map	40
2.4 DMA Channels	41
2.5 PCI Configuration Space Map	41
2.6 Interrupts	42
2.7 PCI Interrupt Routing Map	43
2.8 Connectors	45
2.8.1 Back Panel Connectors	46
2.8.2 Internal I/O Connectors	47
2.8.3 External I/O Connectors	52
2.9 Jumper Blocks	56
2.9.1 Front Panel Audio Connector/Jumper Block	56
2.9.2 BIOS Setup Configuration Jumper Block	57
2.10 Mechanical Considerations	58
2.10.1 I/O Shield	59
2.11 Electrical Considerations	60
2.11.1 DC Loading	60
2.11.2 Add-in Board Considerations	60
2.11.3 Fan Connector Current Capability	60
2.11.4 Power Supply Considerations	61
2.12 Thermal Considerations	61
2.13 Reliability	63
2.14 Environmental	63
2.15 Regulatory Compliance	64
2.15.1 Safety Regulations	64
2.15.2 EMC Regulations	64
2.15.3 European Union Declaration of Conformity Statement	65
2.15.4 Product Ecology Statements	65
2.15.5 Product Certification Markings (Board Level)	66
3 Overview of BIOS Features	67
3.1 Introduction	67
3.2 BIOS Flash Memory Organization	68
3.3 Resource Configuration	68
3.3.1 PCI Autoconfiguration	68
3.3.2 PCI IDE Support	69
3.4 System Management BIOS (SMBIOS)	69
3.5 Legacy USB Support	70
3.6 BIOS Updates	70
3.6.1 Language Support	71
3.6.2 Custom Splash Screen	71
3.7 Boot Options	71
3.7.1 CD-ROM Boot	71
3.7.2 Network Boot	71
3.7.3 Booting Without Attached Devices	72
3.7.4 Changing the Default Boot Device During POST	72
3.8 Fast Booting Systems with Intel® Rapid BIOS Boot	73
3.8.1 Peripheral Selection and Configuration	73
3.8.2 Intel Rapid BIOS Boot	73
3.9 BIOS Security Features	74
4 Error Messages and Beep Codes	75
4.1 BIOS Error Messages	75
4.2 Port 80h POST Codes	77
4.3 Bus Initialization Checkpoints	81
4.4 Speaker	82