Intel D845GVFN Product Specification - Page 51

Add-in Board and Peripheral Interface Connectors

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Technical Reference 2.8.2.3 Add-in Board and Peripheral Interface Connectors Figure 6 shows the location of the add-in board connector and peripheral connectors for the Desktop Board D845GVFN. Note the following considerations for the PCI bus connectors: • All of the PCI bus connectors are bus master capable. • SMBus signals are routed to PCI bus connector 2, enabling PCI bus add-in boards with SMBus support to access sensor data on the desktop board. The SMBus signals are as follows: ⎯ The SMBus clock line is connected to pin A40. ⎯ The SMBus data line is connected to pin A41. A BC 2 1 2 1 F E 40 39 2 40 39 1 D 34 33 OM17300 Item A B C D E F Description PCI bus connector 3 PCI bus connector 2 PCI bus connector 1 Diskette drive Primary IDE Secondary IDE Figure 6. Add-in Board and Peripheral Interface Connectors 51

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Technical Reference
51
2.8.2.3
Add-in Board and Peripheral Interface Connectors
Figure 6 shows the location of the add-in board connector and peripheral connectors for the
Desktop Board D845GVFN.
Note the following considerations for the PCI bus connectors:
•
All of the PCI bus connectors are bus master capable.
•
SMBus signals are routed to PCI bus connector 2, enabling PCI bus add-in boards with SMBus
support to access sensor data on the desktop board.
The SMBus signals are as follows:
⎯
The SMBus clock line is connected to pin A40.
⎯
The SMBus data line is connected to pin A41.
OM17300
A
2
40
39
40
39
1
F
D
E
2
33
34
1
2
B
C
Item
Description
A
PCI bus connector 3
B
PCI bus connector 2
C
PCI bus connector 1
D
Diskette drive
E
Primary IDE
F
Secondary IDE
Figure 6.
Add-in Board and Peripheral Interface Connectors