Intel S5500HV Product Specification - Page 25

Mb, 512 Mb and 4 Gb DRAM technologies; x4 DRAM on UDIMM and Quad rank

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Functional Architecture Intel® Server Board S5500HV/Intel® Server System SR1670HV TPS 3.2.1.1.2 Supported UDIMM configurations: Table 4 Supported UDIMM configurations DIMM DIMMs DIMM Type Speeds Ranks per DIMM Population Rules Slots per Populated Channel per Channel 2 1 Unbuffered DDR3 800, SR or DR 1. Any combination of x8 UDIMMs with (with or without 1066, 1Gb or 2Gb DRAM Density ECC) 1333 2 2 Unbuffered DDR3 800, Mixing SR, DR (with or without 1066 ECC) ƒ 256 Mb, 512 Mb and 4 Gb DRAM technologies; x4 DRAM on UDIMM and Quad rank UDIMM are not supported ƒ Mixing ECC and non-ECC UDIMMs anywhere on the platform will force system to run in non-ECC mode ƒ No RAS support for non-ECC UDIMMs ƒ No x4 SDDC support with UDIMM w/ECC, however x8 SDDC is supported in lock step mode with x8 UDIMMs w/ECC Note: Although non-ECC memory can be used on this server board, Intel does not plan to validate and strongly discourages their use in a working server environment. When installing DIMMs, the following population rules should be followed to deliver best performance ƒ Maximize number of channels populated first ƒ Balanced DIMM population across channels and sockets. Revision 1.2 Intel Confidential 16 Intel order number E69391-006

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Functional Architecture
Intel® Server Board S5500HV/Intel® Server System SR1670HV TPS
Revision 1.2
Intel Confidential
16
Intel order number E69391-006
3.2.1.1.2
Supported UDIMM configurations:
Table 4 Supported UDIMM configurations
DIMM
Slots per
Channel
DIMMs
Populated
per Channel
DIMM Type
Speeds
Ranks per DIMM
Population Rules
2
1
Unbuffered DDR3
(with or without
ECC)
800,
1066,
1333
SR or DR
2
2
Unbuffered DDR3
(with or without
ECC)
800,
1066
Mixing SR, DR
1. Any combination of x8 UDIMMs with
1Gb or 2Gb DRAM Density
±
256 Mb, 512 Mb and 4 Gb DRAM technologies; x4 DRAM on UDIMM and Quad rank
UDIMM are not supported
±
Mixing ECC and non-ECC UDIMMs anywhere on the platform will force system to run in
non-ECC mode
±
No RAS support for non-ECC UDIMMs
±
No x4 SDDC support with UDIMM w/ECC, however x8 SDDC is supported in lock step
mode with x8 UDIMMs w/ECC
Note:
Although non-ECC memory can be used on this server board, Intel does not plan to
validate and strongly discourages their use in a working server environment.
When installing DIMMs, the following population rules should be followed to deliver best
performance
±
Maximize number of channels populated first
±
Balanced DIMM population across channels and sockets.