Intel S5500HV Product Specification - Page 27

Functional Architecture Intel® Server Board S5500HV/Intel® Server System SR1670HV TPS Mirrored Channel Mode In Mirrored Channel Mode, the memory controller supports mirroring across channels, but not across CPU sockets. The contents are mirrored between the first 2 channels of a given processor. For CPU1, mirrored slot pairs include {A1, B1} and {A2, B2}. For CPU2, the mirrored slot pairs include {D1, E1} and {D2, E2}. The sockets of the 3rd channel of each CPU are not used in this mode. D 2 D 1 E 2 E 1 F 2 F 1 CPU 2 Intel® Xeon® Processor 5500 Series Intel® Xeon® Processor 5500 Series CPU 1 A2 A1 B2 B1 C2 C1 Figure 10. Mirror Channel Mode Memory Population Mirrored channel mode requires the following memory population rules: ƒ Channel 0 and Channel 1 of a given processor must be populated identically. ƒ DIMM slot populations within a channel do not have to be identical, but the same DIMM slot location across Channel 0 and Channel 1 must be populated the same. ƒ For example; DIMM slots A1 and B1 must have identical DIMMs installed to be mirrored together. DIMM slots A2 and B2 must have identical DIMMs installed to be mirrored together. However the DIMMs used in mirrored pair {A1, B1} can be different than those used in mirrored pair {A2, B2}. ƒ With two processors installed, DIMM slots associated with each processor must have a valid mirroring configuration for memory channels 0 and 1. However, the memory configuration of each processor can be different from the other. ƒ The exception to this rule is that one processor has no memory installed. Because of the associated latency, this is NOT a recommended operating mode. Revision 1.2 Intel Confidential 18 Intel order number E69391-006