Intel S5500HV Product Specification - Page 28

Intel, Chipset IOH, 82801Jx I/O Controller Hub ICH10R

Page 28 highlights

Intel® Server Board S5500HV/Intel® Server System SR1670HV TPS Functional Architecture The following table illustrates possible DIMM configurations that can be mirrored, with the following assumptions: Two processors are installed; all installed DIMMs are identical. Table 6. Supported Mirrored DIMM Population A1 A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Mirroring Possible? Yes Yes Yes Yes Yes 3.3 Intel® 5500 Chipset IOH The Intel® 5500 Chipset I/O Hub (IOH) provides a connection point between various I/O components and Intel® QuickPath Interconnect (Intel® QPI) based processors. It is capable of interfacing with up to 24 PCI Express* lanes, which can be configured in various combinations of x4, x8, x16 and limited x2 and x1 devices. On the Intel Server Board S5500HV the IOH provides the following: ƒ Two Intel® QuickPath Interconnect (Intel® QPI) interfaces ƒ One X16 PCI Express* Gen 2 port supporting a single PCI Express Gen2 compliant X16 riser card slot. (Compliant to the PCI Express Base Specification, Revision 2.0) ƒ One X4 ESI link interface to the I/O controller hub Intel® ICH10R 3.4 Intel® 82801Jx I/O Controller Hub (ICH10R) The server board utilizes features of the Intel® 82801Jx I/O Controller Hub (ICH10R). Supported features include the following: ƒ PCI Express* Base Specification, Revision 1.1 support ƒ PCI Local Bus Specification, Revision 2.3 support for 33-MHz PCI operations (supports up to four REQ#/GNT# pairs) ƒ ACPI Power Management Logic Support, Revision 3.0a ƒ Enhanced DMA controller, interrupt controller, and timer functions ƒ Integrated Serial ATA host controllers with independent DMA operation on up to four ports and AHCI support ƒ USB host interface with support for four USB 2.0 ports; Two external, two internal ƒ System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices ƒ Low Pin Count (LPC) interface support ƒ Firmware Hub (FWH) interface support ƒ Serial Peripheral Interface (SPI) support 19 Intel Confidential Revision 1.2 Intel order number E69391-006

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Intel® Server Board S5500HV/Intel® Server System SR1670HV TPS
Functional Architecture
19
Intel Confidential
Revision 1.2
Intel order number E69391-006
The following table illustrates possible DIMM configurations that can be mirrored, with the
following assumptions: Two processors are installed; all installed DIMMs are identical.
Table 6. Supported Mirrored DIMM Population
A1
A2
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
Mirroring
Possible?
;
;
Yes
;
;
;
;
Yes
;
;
;
;
Yes
;
;
;
;
;
;
Yes
;
;
;
;
;
;
;
;
Yes
3.3
Intel
®
5500 Chipset IOH
The Intel
®
5500 Chipset I/O Hub (IOH) provides a connection point between various I/O
components and Intel
®
QuickPath Interconnect (Intel
®
QPI) based processors. It is capable of
interfacing with up to 24 PCI Express* lanes, which can be configured in various combinations
of x4, x8, x16 and limited x2 and x1 devices.
On the Intel Server Board S5500HV the IOH provides the following:
±
Two Intel
®
QuickPath Interconnect (Intel
®
QPI) interfaces
±
One X16 PCI Express* Gen 2 port supporting a single PCI Express Gen2 compliant X16
riser card slot. (Compliant to the PCI Express Base Specification, Revision 2.0)
±
One X4 ESI link interface to the I/O controller hub Intel
®
ICH10R
3.4
Intel
®
82801Jx I/O Controller Hub (ICH10R)
The server board utilizes features of the Intel
®
82801Jx I/O Controller Hub (ICH10R). Supported
features include the following:
±
PCI Express* Base Specification
, Revision 1.1 support
±
PCI Local Bus Specification
, Revision 2.3 support for 33-MHz PCI operations (supports
up to four REQ#/GNT# pairs)
±
ACPI Power Management Logic Support
, Revision 3.0a
±
Enhanced DMA controller, interrupt controller, and timer functions
±
Integrated Serial ATA host controllers with independent DMA operation on up to four
ports and AHCI support
±
USB host interface with support for four USB 2.0 ports; Two external, two internal
±
System Management Bus (SMBus) Specification
, Version 2.0 with additional support for
I
2
C devices
±
Low Pin Count (LPC) interface support
±
Firmware Hub (FWH) interface support
±
Serial Peripheral Interface (SPI) support