Intel S5500HV Product Specification - Page 43

INT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch

Page 43 highlights

Platform Management Intel® Server Board S5500HV/Intel® Server System SR1670HV TPS Message Displayed 05 06 08 C0 C1 C2 C5 C6 C7 0A 0B 0C 0E 13 20 24 2A 2C 2E 31 33 37 38 39 3A 3B 3C 40 50 60 75 78 84 85 87 checksum is OK. Message Description Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table Do R/W test to CH-2 count reg. Intialize CH-0 as system timer. Install the POST INT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to POST INT1Ch handler block Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after auto detection of KB/MS Early CPU init start - disable cache - init local APIC Setup boot strap processor information Setup boot strap processor for POST Enumerate and set up application processors Re-enable cache for boot strap processor Early CPU init exit Initializes the 8042 compatible key board controller Detects the presence of PS/2 mouse Detects the presence of keyboard in KBC port Testing and initialization of different input devices. Also update the kernel variables. Traps the INT09h vector so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and silent logo modules Early POST initialization of chipset registers. Initialize system management interrupt Uncompress and initialize any platform specific BIOS modules Initializes different devices through DIM. Initializes different devices. Detects and initializes video adapter installed in the system that have option ROMs Initializes all the output devices Allocate memory for ADM module and uncompress itl. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module. Initializes the silent boot module. Set the window for displaying text information Display sign-on message, CPU information, setup key message, and OEM specific information Initializes different devices through DIM. Initializes DMAC-1 & DMAC-2 Initialize RTC date/time Test for total memory installed in the system. Also check for DEL or ESC keys to limit memory test. Display total memory in the system. Mid POST initialization of chipset registers Detect different devices successfully installed in the system and update the BDA, EBDA... etc. Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed. Initializes NUM-LOCK status and programs the KBD typematic rate Initialize int-13 and prepare for IPL detection Initializes IPL devices controlled by BIOS and option ROMs Log errors encountered during POST Display errors to the user and gets the user response for error Execute BIOS Setup if needed/requested Revision 1.2 Intel Confidential 34 Intel order number E69391-006

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Platform Management
Intel® Server Board S5500HV/Intel® Server System SR1670HV TPS
Revision 1.2
Intel Confidential
34
Intel order number E69391-006
Message Displayed
Message Description
checksum is OK.
05
Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table
06
Do R/W test to CH-2 count reg. Intialize CH-0 as system timer. Install the POST
INT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch
vector to POST INT1Ch handler block
08
Initializes the CPU. The BAT test is being done on KBC. Program the keyboard
controller command byte is being done after auto detection of KB/MS
C0
Early CPU init start – disable cache – init local APIC
C1
Setup boot strap processor information
C2
Setup boot strap processor for POST
C5
Enumerate and set up application processors
C6
Re-enable cache for boot strap processor
C7
Early CPU init exit
0A
Initializes the 8042 compatible key board controller
0B
Detects the presence of PS/2 mouse
0C
Detects the presence of keyboard in KBC port
0E
Testing and initialization of different input devices. Also update the kernel variables.
Traps the INT09h vector so that the POST INT09h handler gets control for IRQ1.
Uncompress all available language, BIOS logo, and silent logo modules
13
Early POST initialization of chipset registers.
20
Initialize system management interrupt
24
Uncompress and initialize any platform specific BIOS modules
2A
Initializes different devices through DIM.
2C
Initializes different devices. Detects and initializes video adapter installed in the
system that have option ROMs
2E
Initializes all the output devices
31
Allocate memory for ADM module and uncompress itl. Give control to ADM module
for initialization. Initialize language and font modules for ADM. Activate ADM
module.
33
Initializes the silent boot module. Set the window for displaying text information
37
Display sign-on message, CPU information, setup key message, and OEM specific
information
38
Initializes different devices through DIM.
39
Initializes DMAC-1 & DMAC-2
3A
Initialize RTC date/time
3B
Test for total memory installed in the system. Also check for DEL or ESC keys to
limit memory test. Display total memory in the system.
3C
Mid POST initialization of chipset registers
40
Detect different devices successfully installed in the system and update the BDA,
EBDA… etc.
50
Programming the memory hole or any kind of implementation that needs an
adjustment in system RAM size if needed.
60
Initializes NUM-LOCK status and programs the KBD typematic rate
75
Initialize int-13 and prepare for IPL detection
78
Initializes IPL devices controlled by BIOS and option ROMs
84
Log errors encountered during POST
85
Display errors to the user and gets the user response for error
87
Execute BIOS Setup if needed/requested