Intel SR2520SAFNA User Guide - Page 98
Table 8. Diagnostic LED POST Code Decoder
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Table 8. Diagnostic LED POST Code Decoder Checkpoint Diagnostic LED Decoder Description G=Green, R=Red, A=Amber MSB LSB Host Processor 0x10h OFF 0x11h 0x12h 0x13h Chipset 0x21h Memory 0x22h OFF OFF OFF OFF OFF 0x23h 0x24h OFF OFF 0x25h OFF 0x26h 0x27h 0x28h OFF OFF G OFF OFF R OFF OFF A OFF G R OFF G A Power-on initialization of the host processor (bootstrap processor) Host processor cache initialization (including AP) Starting application processor initialization SMM initialization OFF R G Initializing a chipset component OFF A OFF A G R G R G A G A OFF R OFF G OFF G OFF G OFF Reading configuration data from memory (SPD on DIMM) Detecting presence of memory Programming timing parameters in the memory controller Configuring memory parameters in the memory controller Optimizing memory controller settings Initializing memory, such as ECC init Testing memory 76 Intel® Server System SR2520SA User's Guide