Sony STR-DB1070 Service Manual - Page 48

Sony STR-DB1070 - Fm Stereo/fm-am Receiver Manual

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Page 48 highlights

STR-DB870/DB1070 Pin No. 60, 61 62 63 64 65 66 67, 68 69, 70 71 72 73 74 75 76 77, 78 79 80 81 82 83 84 85 86 87 to 89 90 91 92 to 94 95 96 97 98 99 100 101 102 103, 104 105, 106 107, 108 109 110 111 112 113, 114 115, 116 117 118, 119 Pin Name SDO1, SDO2 KFSIO LRCKO BCKO VDDI VSS D18, D17 A10, A9 CAS RAS VDDI HDIN HCLK HCS A8, A7 D16 D15 VSS HDOUT HACN CSO WEO A6 D14 to D12 VDDE VSS D11 to D9 A5 VDDI TCK TDI TDO TMS XTRST VSS D8, D7 A4, A3 GP10, GP9 VDDI GP8 GP7 GP6 A2, A1 D6, D5 VSS GP5, GP4 48 I/O Description O Audio serial data output to the D/A converter (IC1201) I/O Audio clock signal (384fs/256fs) in/out terminal O L/R sampling clock signal output to the D/A converter (IC1201, 1202) O Bit clock signal output to the D/A converter (IC1201, 1202) - Power supply terminal (+2.5V) - Ground terminal I/O Two-way data bus with the S-RAM (IC1602) O Address signal output to the S-RAM (IC1602) O Column address strobe signal output terminal Not used (open) O Row address strobe signal output terminal Not used (open) - Power supply terminal (+2.5V) I Host serial data input from the system contrller (IC1703) I Host clock signal input from the system contrller (IC1703) I Host chip select input from the system contrller (IC1703) O Address signal output to the S-RAM (IC1602) I/O Two-way data bus with the S-RAM (IC1602) I/O Two-way data bus terminal Not used (open) - Ground terminal O Host serial data input from the system contrller (IC1703) O Host acknowledge signal output to the system controller (IC1703) O Chip select signal output to the S-RAM (IC1602) O Write enable signal output to the S-RAM (IC1602) O Address signal output to the S-RAM (IC1602) I/O Two-way data bus terminal Not used (open) - Power supply terminal (+3.3V) - Ground terminal I/O Two-way data bus terminal Not used (open) O Address signal output to the S-RAM (IC1602) - Power supply terminal (+2.5V) I Emulation clock signal input terminal Not used (open) I Emulation data input terminal Not used (open) O Emulation data input terminal Not used (open) I Emulation data input start/end select Not used (open) I Emulation break signal input terminal Not used (open) - Ground terminal I/O Two-way data bus terminal Not used (open) O Address signal output to the S-RAM (IC1602) - Not used (open) - Power supply terminal (+2.5V) - Not used (open) I Serial clock signal input terminal - Not used (open) O Address signal output to the S-RAM (IC1602) I/O Two-way data bus terminal Not used (open) - Ground terminal - Not used (open)

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48
STR-DB870/DB1070
Pin No.
Pin Name
I/O
Description
60, 61
SDO1, SDO2
O
Audio serial data output to the D/A converter (IC1201)
62
KFSIO
I/O
Audio clock signal (384fs/256fs) in/out terminal
63
LRCKO
O
L/R sampling clock signal output to the D/A converter (IC1201, 1202)
64
BCKO
O
Bit clock signal output to the D/A converter (IC1201, 1202)
65
VDDI
—
Power supply terminal (+2.5V)
66
VSS
—
Ground terminal
67, 68
D18, D17
I/O
Two-way data bus with the S-RAM (IC1602)
69, 70
A10, A9
O
Address signal output to the S-RAM (IC1602)
71
CAS
O
Column address strobe signal output terminal
Not used (open)
72
RAS
O
Row address strobe signal output terminal
Not used (open)
73
VDDI
—
Power supply terminal (+2.5V)
74
HDIN
I
Host serial data input from the system contrller (IC1703)
75
HCLK
I
Host clock signal input from the system contrller (IC1703)
76
HCS
I
Host chip select input from the system contrller (IC1703)
77, 78
A8, A7
O
Address signal output to the S-RAM (IC1602)
79
D16
I/O
Two-way data bus with the S-RAM (IC1602)
80
D15
I/O
Two-way data bus terminal
Not used (open)
81
VSS
—
Ground terminal
82
HDOUT
O
Host serial data input from the system contrller (IC1703)
83
HACN
O
Host acknowledge signal output to the system controller (IC1703)
84
CSO
O
Chip select signal output to the S-RAM (IC1602)
85
WEO
O
Write enable signal output to the S-RAM (IC1602)
86
A6
O
Address signal output to the S-RAM (IC1602)
87 to 89
D14 to D12
I/O
Two-way data bus terminal
Not used (open)
90
VDDE
—
Power supply terminal (+3.3V)
91
VSS
—
Ground terminal
92 to 94
D11 to D9
I/O
Two-way data bus terminal
Not used (open)
95
A5
O
Address signal output to the S-RAM (IC1602)
96
VDDI
—
Power supply terminal (+2.5V)
97
TCK
I
Emulation clock signal input terminal
Not used (open)
98
TDI
I
Emulation data input terminal
Not used (open)
99
TDO
O
Emulation data input terminal
Not used (open)
100
TMS
I
Emulation data input start/end select
Not used (open)
101
XTRST
I
Emulation break signal input terminal
Not used (open)
102
VSS
—
Ground terminal
103, 104
D8, D7
I/O
Two-way data bus terminal
Not used (open)
105, 106
A4, A3
O
Address signal output to the S-RAM (IC1602)
107, 108
GP10, GP9
—
Not used (open)
109
VDDI
—
Power supply terminal (+2.5V)
110
GP8
—
Not used (open)
111
GP7
I
Serial clock signal input terminal
112
GP6
—
Not used (open)
113, 114
A2, A1
O
Address signal output to the S-RAM (IC1602)
115, 116
D6, D5
I/O
Two-way data bus terminal
Not used (open)
117
VSS
—
Ground terminal
118, 119
GP5, GP4
—
Not used (open)