Asus P8Z77-I DELUXE P8Z77-I DELUXE User's Manual - Page 77
Channel A DIMM Control [Enable Both DIMMS]
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tRR (DR) [Auto] Configuration options: [Auto] [1 DRAM Clock] - [8 DRAM Clock] tRRSR [Auto] Configuration options: [Auto] [4 DRAM Clock] - [7 DRAM Clock] tWW (DD) [Auto] Configuration options: [Auto] [1 DRAM Clock] - [8 DRAM Clock] tWW (DR) [Auto] Configuration options: [Auto] [1 DRAM Clock] - [8 DRAM Clock] tWWSR [Auto] Configuration options: [Auto] [4 DRAM Clock] - [7 DRAM Clock] MISC MRC Fst Boot [Enabled] Configuration options: [Enabled] [Disabled] DRAM CLK Period [Auto] Configuration options: [Auto] [1 DRAM Clock] - [14 DRAM Clock] Transmitter Slew (CHA) [Auto] Configuration options: [Auto] [1 DRAM Clock] - [7 DRAM Clock] Transmitter Slew (CHB) [Auto] Configuration options: [Auto] [1 DRAM Clock] - [7 DRAM Clock] Receiver Slew (CHA) [Auto] Configuration options: [Auto] [1 DRAM Clock] - [7 DRAM Clock] Receiver Slew (CHB) [Auto] Configuration options: [Auto] [1 DRAM Clock] - [7 DRAM Clock] MCH Duty Sense (CHA) [Auto] Configuration options: [Auto] [1 DRAM Clock] - [31 DRAM Clock] MCH Duty Sense (CHB) [Auto] Configuration options: [Auto] [1 DRAM Clock] - [31 DRAM Clock] Channel A DIMM Control [Enable Both DIMMS] Configuration options: [Enable Both DIMMS] [Disable DIMM0] [Disable DIMM1] [Disable Both DIMMS] Channel B DIMM Control [Enable Both DIMMS] Configuration options: [Enable Both DIMMS] [Disable DIMM0] [Disable DIMM1] [Disable Both DIMMS] DRAM Read Additional Swizzle [Auto] Configuration options: [Auto] [Enabled] [Disabled] DRAM Write Additional Swizzle [Auto] Configuration options: [Auto] [Enabled] [Disabled] Chapter 3 ASUS P8Z77-I DELUXE 3-11