Asus Terminator K7 E732 MANUAL TERMINATOR K7 English V1.0 - Page 92
PCI to DRAM Prefetch [Enabled]
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SDRAM RAS to CAS Delay This controls the latency between the SDRAM active command and the read/write command. NOTE: This field will only be adjustable when SDRAM Configuration is set to [User Define]. PCI Master Read Caching [Disabled] Default: [Disabled] Leave on default setting. Configuration options: [Disabled] [Enabled] Delayed Transaction [Disabled] Default: [Disabled] Leave on default setting. Enabled, this frees the PCI Bus when the CPU is accessing 8-bit ISA devices that normally consume about 5060 PCI Clocks without PCI delayed transaction. Select [Disabled] for ISA devices that are not PCI 2.1 compliant. Configuration options: [Disabled] [Enabled] PCI to DRAM Prefetch [Enabled] Configuration options: [Disabled] [Enabled] Byte Merge [Disabled] To optimize the data transfer on PCI, this merges a sequence of individual memory writes (bytes or words) into a single 32-bit block of data. However, byte merging may only be done when the bytes within a data phase are in a prefetchable address range. Configuration options: [Disabled] [Enabled] DRAM Read Latch Delay [Auto] Configuration options: [-0.01 ns] [0.75 ns]...[Auto] Memory Early/Delay Write [Auto] Configuration options: [0.0 ns] [0.5 ns]...[Auto] DIMM Interleave Setting [Auto] Configuration options: [Auto] [Disabled] VGA Shared Memory Size This size cannot exceed the last memory bank size in the system. If there is only one DRAM bank in the system, this size is set to half of this DRAM bank size automatically. Select Display Device to select the display device for next boot. 92 Chapter 5: BIOS Information