Biostar M7VKQ M7VKQ user's manual - Page 52
SDRAM Cycle Length, Bank Interleave, Memory Hole, System BIOS Cacheable, Video RAM Cacheable
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Chapter 2 BIOS Setup SDRAM Cycle Length When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the system designer. The Choices: 3 (default), 2. Bank Interleave This item allows you to enable or disable the bank interleave feature. The Choices: Disabled (default), 2Bank, 4Bank. Memory Hole When enabled, you can reserve an area of system memory for ISA adapter ROM. When this area is reserved, it cannot be cached. Refer to the user documentation of the peripheral you are installing for more information. The Choices: Disabled (default), 15M-16M. System BIOS Cacheable When enabled, accesses to system BIOS ROM addressed at F0000H-FFFFFH is cached, provided that the cache controller is enabled. The Choices: Enabled (default), Disabled. Video RAM Cacheable Select Enabled allows caching of the video BIOS, resulting in better system performance. However, if any program writes to this memory area, a system error may result. The Choices: Enabled (default), Disabled. AGP Aperture Size Select the size of the Accelerated Graphics Port (AGP) aperture. The aperture is a portion of the PCI memory address range dedicated for graphics memory address space. Host cycles that hit the aperture range are forwarded to the AGP without any translation. The Choices: 64M (default),256M, 128M, 64M, 32M, 16M, 8M, 4M. AGP Mode This item allows you to select the AGP Mode. The Choices: 4X (default), 2X, 1X. 2-15