Biostar M7VKQ M7VKQ user's manual - Page 68

Assign IRQ For USB, PCI Master Pipeline Req, P2C/C2P Concurrency, Fast R-W Turn Around

Get Biostar M7VKQ PDF manuals and user guides View all Biostar M7VKQ manuals
Add to My Manuals
Save this manual to your list of manuals

Page 68 highlights

Chapter 2 BIOS Setup Assign IRQ For USB Lets the user choose which IRQ to assign for the USB. The Choices: Enabled (default), Disabled. PCI Master Pipeline Req This item allows you to enable/disable the PCI master pipeline request feature. The Choices: Enabled (default), Disabled. P2C/C2P Concurrency This item allows you to enable/disable the PCI to CPU, CPU to PCI concurrency. The Choices: Enabled (default), Disabled. Fast R-W Turn Around This item controls the DRAM timing. It allows you to enable/disable the fast read/write turn around. The Choices: Disabled (default), Enabled. PCI Dynamic Bursting When Enabled, every write transaction goes to the write buffer. Burstable transactions the burst on the PCI bus and nonburstable transactions don't. The Choices: Enabled (default), Disabled. PCI Master 0 Ws Write When Enabled, writes to the PCI bus are executed with zero-wait states. The Choices: Enabled (default), Disabled. PCI Delay Transaction The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification. The Choices: Enabled (default), Disabled. 2-31

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
Chapter 2
BIOS Setup
2-31
Assign IRQ For USB
Lets the user choose which IRQ to assign for the USB.
The Choices: Enabled
(default), Disabled.
PCI Master Pipeline Req
This item allows you to enable/disable the PCI master pipeline request feature.
The Choices: Enabled
(default), Disabled.
P2C/C2P Concurrency
This item allows you to enable/disable the PCI to CPU, CPU to PCI concurrency.
The Choices: Enabled
(default)
,
Disabled.
Fast R-W Turn Around
This item controls the DRAM timing. It allows you to enable/disable the fast
read/write turn around.
The Choices: Disabled
(default)
,
Enabled.
PCI Dynamic Bursting
When Enabled, every write transaction goes to the write buffer. Burstable
transactions the burst on the PCI bus and nonburstable transactions don't.
The Choices: Enabled
(default), Disabled.
PCI Master 0 Ws Write
When Enabled, writes to the PCI bus are executed with zero-wait states.
The Choices: Enabled
(default)
,
Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification.
The Choices: Enabled
(default), Disabled.