Epson Apex 386SX/16 Canadian Product User Manual - Page 120

Appendix, Table, Address, Channel, Channels, Through

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The addresses for the page register are as follows: Table 6-6: I/O Hex Address Address generation for the DMA channels is as follows: Table 6-7: DMA Channel 3 Through 0 Note: To generate the addressing signal "byte high enable" (BHE), invert address line AO. Table 6-8: DMA Channels 7 Through 5 Note: The BHE and A0 addressing signals are forced to a logical 0. DMA channel addresses do not increase or decrease through page boundaries 64KB for channels 0 through 3 and 128KB for channels 5 through 7). 22 Chapter 6:Appendix

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22
Chapter
6:
Appendix
The
addresses
for
the
page
register
are
as
follows:
Table
6-6:
I/O
Hex
Address
Address
generation
for
the
DMA
channels
is
as
follows:
Table
6-7: DMA
Channel
3 Through 0
Note:
To
generate
the
addressing
signal
“byte
high
enable”
(BHE),
invert
address
line
AO.
Table
6-8:
DMA
Channels
7
Through
5
Note:
The
BHE
and
A0
addressing
signals
are
forced
to
a
logical
0.
DMA
channel
addresses
do
not
increase
or
decrease
through
page
boundaries
64KB
for
channels
0
through
3
and
128KB
for
channels
5
through
7).