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Hitachi HTS541040G9AT00 Specifications - Page 78

Alternate Status Register, Command Register, Data Register

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10.1 Alternate Status Register Table 38: Alternate Status Register 7 6 5 4 3 2 1 0 BSY RDY DF DSC DRQ COR IDX ERR This register contains the same information as the Status Register. The only difference between this register and the Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a pending interrupt. See Section 10.13 "Status Register," on page 67 for the definition of the bits in this register. 10.2 Command Register This register contains the command code being sent to the device. Command execution begins immediately after this register is written. The command set is shown in Table 58: "Command Set (1 of 2)," on page 97 and Table 59: "Command Set (2 of 2)," on page 98. All other registers required for the command must be set up before writing to the Command Register. 10.3 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command and the configuration information is transferred on an Identify Device command. All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO only. The register contains valid data only when DRQ = 1 is in the Status Register. Travelstar 5K100 Hard Disk Drive Specification 64

Section	Page
1.0 General	15
1.1 Introduction	15
1.2 References	15
1.3 Abbreviations	15
1.4 Caution	17
1.5 Drive handling precautions	18
2.0 Outline of the drive	19
3.0 Fixed-disk subsystem description	23
3.1 Control electronics	23
3.2 Head disk assembly data	23
4.0 Drive characteristics	25
4.1 Formatted capacity	25
4.2 Data sheet	25
4.3 Cylinder allocation	26
4.4 Performance characteristics	28
4.4.1 Command overhead	28
4.4.2 Mechanical positioning	28
4.4.3 Operating modes	30
5.0 Data integrity	33
5.1 Data loss at power off	33
5.2 Write Cache	33
5.3 Equipment status	33
5.4 WRITE safety	34
5.5 Data buffer test	34
5.6 Error recovery	34
5.7 Automatic reallocation	34
5.8 ECC	35
6.0 Specification	37
6.1 Environment	37
6.1.1 Temperature and humidity	37
6.1.2 Radiation noise	39
6.1.3 Conductive noise	39
6.1.4 Magnetic fields	39
6.2 DC power requirements	39
6.2.1 Power consumption efficiency	40
6.3 Reliability	40
6.3.1 Data Reliability	40
6.3.2 Failure prediction (S.M.A.R.T.)	41
6.3.3 Cable noise interference	41
6.3.4 Service life and usage condition	41
6.3.5 Preventive maintenance	41
6.3.6 Load/unload	41
6.4 Mechanical specifications	44
6.4.1 Physical dimensions and weight	44
6.4.2 Mounting hole locations	45
6.4.3 Connector and jumper description	45
6.4.4 Mounting orientation	45
6.4.5 Load/unload mechanism	46
6.5 Vibration and shock	47
6.5.1 Operating vibration	47
6.5.2 Nonoperating vibration	47
6.5.3 Operating shock	48
6.5.4 Nonoperating shock	48
6.6 Acoustics	49
6.6.1 Sound power levels	49
6.6.2 Discrete tone penalty	49
6.7 Identification labels	50
6.8 Electromagnetic compatibility	50
6.8.1 CE mark	50
6.8.2 C-TICK mark	50
6.8.3 BSMI mark	50
6.8.4 MIC mark	50
6.9 Safety	50
6.9.1 UL and CSA approval	51
6.9.2 IEC compliance	51
6.9.3 German safety mark	51
6.9.4 Flammability	51
6.9.5 Secondary circuit protection	51
6.10 Packaging	51
7.0 Electrical interface specification	53
7.1 Cabling	53
7.2 Interface connector	53
7.3 Signal definitions	54
7.4 Signal descriptions	55
7.5 Interface logic signal levels	58
7.6 Reset timings	58
7.7 PIO timings	59
7.8 Multi word DMA timings	60
7.9 Ultra DMA timings	61
7.9.1 Initiating Read DMA	61
7.9.2 Host Pausing Read DMA	62
7.9.3 Host Terminating Read DMA	63
7.9.4 Device Terminating Read DMA	64
7.9.5 Initiating Write DMA	65
7.9.6 Device Pausing Write DMA	66
7.9.7 Device Terminating Write DMA	67
7.9.8 Host Terminating Write DMA	68
7.10 Drive address setting	69
7.11 Addressing of HDD registers	70
8.0 General	73
8.1 Introduction	73
8.2 Terminology	73
9.0 Deviations from standard	75
10.0 Register	77
10.1 Alternate Status Register	78
10.2 Command Register	78
10.3 Data Register	78
10.4 Device Control Register	79
10.5 Drive Address Register	79
10.6 Device Register	80
10.7 Error Register	80
10.8 Features Register	80
10.9 LBA High Register	81
10.10 LBA Low Register	81
10.11 LBA Mid Register	81
10.12 Sector Count Register	81
10.13 Status Register	81
11.0 General	83
11.1 Reset response	83
11.2 Register initialization	84
11.3 Diagnostic and Reset considerations	85
11.4 Power-off considerations	86
11.4.1 Load/Unload	86
11.4.2 Emergency unload	86
11.4.3 Required power-off sequence	86
11.5 Sector Addressing Mode	87
11.5.1 Logical CHS addressing mode	87
11.5.2 LBA addressing mode	87
11.6 Power management features	88
11.6.1 Power mode	88
11.6.2 Power management commands	88
11.6.3 Standby/Sleep command completion time	88
11.6.4 Standby timer	89
11.6.5 Status	89
11.6.6 Interface capability for power modes	89
11.6.7 Initial Power Mode at Power On	89
11.7 Advanced Power Management (ABLE-3) feature	89
11.7.1 Performance Idle Mode	90
11.7.2 Active Idle Mode	90
11.7.3 Low Power Idle Mode	90
11.7.4 Transition time	90
11.8 Interface Power Management Mode (Slumber and Partial)	90
11.9 S.M.A.R.T. Function	91
11.9.1 Attributes	91
11.9.2 Attribute values	91
11.9.3 Attribute thresholds	91
11.9.4 Threshold exceeded condition	91
11.9.5 S.M.A.R.T. commands	91
11.9.6 S.M.A.R.T. operation with power management modes	92
11.10 Security Mode Feature Set	92
11.10.1 Security mode	92
11.10.2 Security level	92
11.10.3 Password	93
11.10.4 Master Password Revision Code	93
11.10.5 Command table	96
11.11 Protected Area Function	97
11.11.1 Example for operation (In LBA Mode)	97
11.11.2 Set Max security extension commands	98
11.12 Address Offset Feature (vendor specific)	99
11.12.1 Enable/Disable Address Offset Mode	99
11.12.2 Identify Device Data	100
11.12.3 Exceptions in Address Offset Mode	100
11.13 Seek Overlap	101
11.14 Write Cache function	101
11.15 Reassign Function	102
11.15.1 Auto Reassign Function	102
11.16 48-bit Address Feature Set	103
12.0 Command protocol	105
12.1 Data In commands	105
12.2 Data Out Commands	106
12.3 Non-data commands	107
12.4 DMA Data Transfer commands:	109
13.0 Command descriptions	111
13.1 Check Power Mode (E5h/98h)	116
13.2 Device Configuration Overlay (B1h)	117
13.2.1 DEVICE CONFIGURATION RESTORE (subcommand C0h)	117
13.2.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h)	117
13.2.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h)	118
13.2.4 DEVICE CONFIGURATION SET (subcommand C3h)	118
13.3 Execute Device Diagnostic (90h)	120
13.4 Flush Cache (E7h)	121
13.5 Flush Cache EXT (EAh)	122
13.6 Format Track (50h: vendor specific)	123
13.7 Format Unit (F7h: vendor specific)	124
13.8 Identify Device (ECh)	125
13.9 Idle (E3h/97h)	134
13.10 Idle Immediate (E1h/95h)	135
13.11 Initialize Device Parameters (91h)	136
13.12 Read Buffer (E4h)	137
13.13 Read DMA (C8h/C9h)	138
13.14 Read DMA EXT (25h)	140
13.15 Read Log Ext (2Fh)	142
13.15.1 General purpose log Directory	143
13.15.2 Extended comprehensive SMART error log	144
13.15.3 Error Log version	144
13.15.4 Extended Self-test log sector	146
13.16 Read Long (22h/23h)	148
13.17 Read Multiple (C4h)	150
13.18 Read Multiple EXT (29h)	152
13.19 Read Native Max ADDRESS (F8h)	153
13.20 Read Native Max ADDRESS EXT (27h)	154
13.21 Read Sectors (20h/21h)	155
13.22 Read Sector(s) EXT (24h)	156
13.23 Read Verify Sectors (40h/41h)	158
13.24 Ready Verify Sector(s) EXT (42h)	160
13.25 Recalibrate (1xh)	162
13.26 Security Disable Password (F6h)	163
13.27 Security Disable Password (F6h)	164
13.28 Security Erase Unit (F4h)	166
13.29 Security Freeze Lock (F5h)	168
13.30 Security Set Password (F1h)	169
13.31 Security Unlock (F2h)	171
13.32 Seek (7xh)	172
13.33 Sense Condition (F0h: vendor specific)	173
13.34 Set Features (EFh)	174
13.35 Set Max ADDRESS (F9h)	176
13.36 Set Max ADDRESS EXT (37h)	178
13.37 Set Multiple (C6h)	180
13.38 Sleep (E6h/99h)	181
13.39 S.M.A.R.T. Function Set (B0h)	182
13.39.1 S.M.A.R.T. Function Subcommands	183
13.39.2 Device Attribute Data Structure	188
13.39.3 Device Attribute Thresholds data structure	193
13.39.4 S.M.A.R.T Log Directory	194
13.39.5 S.M.A.R.T. error log sector	195
13.39.6 Self-test log data structure	197
13.39.7 Selective self-test log data structure	197
13.39.8 Error reporting	199
13.40 Standby (E2h/96h)	200
13.41 Standby Immediate (E0h/94h)	201
13.42 Write Buffer (E8h)	202
13.43 Write DMA (CAh/CBh)	203
13.44 Write DMA EXT (35h)	205
13.45 Write Long (32h/33h)	207
13.46 Write Multiple (C5h)	209
13.47 Write Multiple EXT (39h)	210
13.48 Write Sectors (30h/31h)	212
13.49 Write Sectors(s) EXT (34h)	214
13.50 Write Verify (3Ch: vendor specific)	215
14.0 Timings	217
15.0 Appendix	219
15.1 Commands Support Coverage	219
15.2 SET FEATURES Commands Support Coverage	221
15.3 Changes from the Travelstar 4K40	222
A	225
B	225
C	225
D	225
E	225
F	225
H	225
I	225
L	225
M	225
N	226
O	226
P	226
R	226
S	226
T	226
U	226
V	226
W	226

Match case Limit results 1 per page

Travelstar 5K100 Hard Disk Drive Specification

10.1

Alternate Status Register

Table 38: Alternate Status Register

This register contains the same information as the Status Register. The only difference between this register and the

Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a

pending interrupt. See Section 10.13 "Status Register," on page 67 for the definition of the bits in this register.

10.2

Command Register

This register contains the command code being sent to the device. Command execution begins immediately after

this register is written. The command set is shown in Table 58:

"Command Set (1 of 2)," on page 97 and Table

59:

"Command Set (2 of 2)," on page 98. All other registers required for the command must be set up before writ-

ing to the Command Register.

10.3

Data Register

This register is used to transfer data blocks between the device data buffer and the host. It is also the register

through which sector information is transferred on a Format Track command and the configuration information is

transferred on an Identify Device command.

All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO

only.

The register contains valid data only when DRQ = 1 is in the Status Register.

BSY

RDY

DSC

DRQ

COR

IDX

ERR