Hitachi HTS541040G9AT00 Specifications - Page 79
Device, Control Register, Drive Address Register - software
UPC - 000059826569
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10.4 Device Control Register Table 39: Device Control Register 7 6 5 4 3 2 1 0 HOB - - - 1 SRST -IEN 0 Bit HOB SRST (RST) -IEN Definitions HOB (high order byte) is defined by the 48-bit Address feature set. A write to any Command Register shall clear the HOB bit to zero. Software Reset. The device is held at reset when RST = 1. Setting RST = 0 again enables the device. To ensure that the device recognizes the reset, the host must set RST = 1 and wait for at least 5 ms before setting RST = 0. Interrupt Enable. When IEN = 0, and the device is selected, the device interrupts to the host will be enabled. When IEN = 1, or the device is not selected, the device interrupts to the host will be disabled. 10.5 Drive Address Register Table 40: Drive Address Register 7 6 5 4 3 HIZ WTG -H3 -H2 -H1 2 1 0 -H0 -DS1 -DS0 This register contains the inverted drive select and head select addresses of the currently selected drive. Bit HIZ -WTG -H3, -H2,H1,-H0-DS1 -DS0 Definitions High Impedance. This bit is not a device and will always be in a high impedance state. Write Gate. This bit is 0 when writing to the disk device is in progress. -H3, -H2,-H1,-H0-Head Select. These four bits are the one's complement of the binary coded address of the currently selected head. Bit -H0 is the least significant. Drive Select 1. The Drive Select bit for device 1 is active low. DS1 = 0 when device 1 (slave) is selected and active. Drive Select 0. The Drive Select bit for device 0 is active low. DS0 = 0 when device 0 (master) is selected and active. Travelstar 5K100 Hard Disk Drive Specification 65