Icom IC-7000 Service Manual - Page 12

The VHF/UHF APC detector circuits (PA unit; D501, D504, D401, D404) detect the forward and reflection signals and convert into DC voltages. The converted DC voltages are combined and applied to the ALC amplifier (pins 1, 2) as "VUFOR" voltage. For the current APC, the driving current at the power amplifiers is detected in the voltages ("ICH" and "ICL") which appear at both terminals of detector resistors (PA unit; R721, R722). The detected voltages are applied to the APC amplifier (IC1601, pins 5-7). When the current of the power amplifier exceeds 22 A, The output voltage from the APC amplifier (IC1601, pin 7) controls the ALC line to prevent excessive current flow. 3-2-12 RF, ALC, SWR METER CIRCUITS (LOGIC UNIT) While transmitting, RF, ALC or SWR meter readings are available and can be selected with the [F3 (MET)] switch. (1) Power meter The "FOR," "VFOR" and "UFOR" voltages are combined to the "FORL" voltage, and it is then applied to the main CPU (IC1302, pin 113) for indicating the TX output power. (2) ALC meter The ALC bias voltage from the buffer amplifier (MAIN unit; IC1601, pin 14) is applied to the main CPU (IC1302, pin 115) via the "ALCL" signal line for indicating the ALC level. (3) SWR meter The "FORL" and "REFL" voltages are applied to the main CPU (IC1302, pins 113, 114) respectively. The main CPU compares the ratio of "FORL" to "REFL" voltage and indicates the SWR for the [ANT1] connector. 3-3 DDS CIRCUITS 3-3-1 GENERAL The DDS unit generates a 1st LO (124.517-594.487 MHz), a 2nd LO (124.032 MHz) and a 3rd LO (438.85 kHz) frequencies. 3-3-2 1ST LO CIRCUIT (DDS UNIT) The 1st LO circuit generates a 1st LO signal based on the system clock that is tripled the 2nd LO frequency. The 124.032 MHz 2nd LO signal is applied to the tripler circuit (Q201) and then passed through the high-pass filter (L205, L206, L210, C206-C210, C217-C219). The filtered signal is amplified at Q211 and then passed through the bandpass filter (FI201). The filtered signal is applied to the DDS IC (IC301) as the 372.096 MHz system clock. The DDS IC generates 38.62189-199.999999 MHz frequency based on the system clock. The output signal from the DDS IC (IC301, pins 20, 21) is applied to the doubler circuit (D301) and then amplified at IC401 (pins 1, 4) after being passed through the low-pass filter (L331, L332, C331, C332, C335). The amplified signal is applied to one of the multiplier circuits which is selected from the readout frequency and then amplified at IC451 (pins 1, 5). The amplified signal is passed through the bandpass filters. The filtered signal is applied to the 1st mixer circuit (MAIN unit) via J851. • FREQUENCY CONSTRUCTION [ANT1] [ANT2] 0.03- 60 MHz 60- 470 MHz 1st mixer IC401 2nd mixer D801 to WFM detector (IC1401) 3rd mixer IC1101 MAIN UNIT 1st IF: 124.487 MHz (WFM: 134.732 MHz) 124.517- 594.487 MHz (1st LO) 2nd IF: 455 kHz 124.032 MHz (2nd LO) to DSP circuit 3rd IF: 16.15 kHz 438.85 kHz (3rd LO) ×2 Q301 DDS UNIT BPF 124.517- 154.486999 MHz ×2 D456 BPF 154.487- 324.486999 MHz ×4 D471 BPF 524.487- 594.487 MHz DDS BPF IC301 FI201 372.096 MHz (system clock) ×3 Q201 LPF BPF FI101 ×5 Q101 AMP. IC61 DDS IC51 24.8064 MHz (system clock) AMP. Q1 Ref. Osc. 24.8064 MHz X1 3 - 7