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Fixed I/O Map

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Intel Desktop Board D915GAV/D915GAG Technical Product Specification 2.4 Fixed I/O Map Table 15. I/O Map Address (hex) Size Description 0000 - 00FF 0170 - 0177 256 bytes 8 bytes Used by the Desktop Board D915GAV/D915GAG. Refer to the ICH6 data sheet for dynamic addressing information. Secondary Parallel ATA IDE channel command block 01F0 - 01F7 8 bytes Primary Parallel ATA IDE channel command block 0228 - 022F (Note 1) 0278 - 027F (Note 1) 02E8 - 02EF (Note 1) 02F8 - 02FF (Note 1) 0374 - 0377 0377, bits 6:0 8 bytes 8 bytes 8 bytes 8 bytes 4 bytes 7 bits LPT3 LPT2 COM4 COM2 Secondary Parallel ATA IDE channel control block Secondary IDE channel status port 0378 - 037F 03E8 - 03EF 03F0 - 03F5 03F4 - 03F7 03F8 - 03FF 04D0 - 04D1 LPTn + 400 0CF8 - 0CFB (Note 2) 0CF9 (Note 3) 0CFC - 0CFF FFA0 - FFA7 FFA8 - FFAF 8 bytes 8 bytes 6 bytes 1 byte 8 bytes 2 bytes 8 bytes 4 bytes 1 byte 4 bytes 8 bytes 8 bytes LPT1 COM3 Diskette channel Primary Parallel ATA IDE channel control block COM1 Edge/level triggered PIC ECP port, LPTn base address + 400h PCI Conventional bus configuration address register Reset control register PCI Conventional bus configuration data register Primary Parallel ATA IDE bus master registers Secondary Parallel ATA IDE bus master registers Notes: 1. Default, but can be changed to another address range 2. Dword access only 3. Byte access only NOTE Some additional I/O addresses are not available due to ICH6 address aliassing. The ICH6 data sheet provides more information on address aliassing. For information about Obtaining the ICH6 data sheet Refer to Section 1.4, page 19 58

Section	Page
Intel® Desktop Boards D915GAV/D915GAG Technical Product Specification	1
Revision History	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Other Common Notations	4
Contents	5
1 Product Description	11
1.1 PCI Bus Terminology Change	11
1.2 Board Differences	11
1.3 Overview	12
1.3.1 Feature Summary	12
1.3.2 Manufacturing Options	13
1.3.3 Board Layouts	14
1.3.4 Block Diagram	18
1.4 Online Support	19
1.5 Processor	19
1.6 System Memory	20
1.6.1 Memory Configurations	22
1.7 Intel® 915G Chipset	26
1.7.1 Intel 915G Graphics Subsystem	26
1.7.2 USB	28
1.7.3 IDE Support	28
1.7.4 Real-Time Clock, CMOS SRAM, and Battery	30
1.8 PCI Express Connectors	30
1.9 I/O Controller	31
1.9.1 Serial Ports	31
1.9.2 Parallel Port	31
1.9.3 Diskette Drive Controller	32
1.9.4 Keyboard and Mouse Interface	32
1.10 Audio Subsystem	32
1.10.1 Audio Subsystem Software	33
1.10.2 Audio Connectors	33
1.10.3 Intel High Definition Audio Subsystem	34
1.11 LAN Subsystem	35
1.11.1 10/100 Mbits/sec LAN Subsystem	35
1.11.2 Gigabit LAN Subsystem	36
1.11.3 Alert Standard Format (ASF) Support	37
1.11.4 LAN Subsystem Software	38
1.12 Hardware Management Subsystem	38
1.12.1 Hardware Monitoring and Fan Control ASIC	38
1.12.2 Thermal Monitoring	39
1.12.3 Fan Monitoring	41
1.12.4 Chassis Intrusion and Detection	41
1.13 Power Management	41
1.13.1 ACPI	41
1.13.2 Hardware Support	44
1.14 Trusted Platform Module (Optional)	48
1.14.1 System Requirements	48
1.14.2 Warning of Potential Data Loss	48
1.14.3 Security Precautions	49
1.14.4 Trusted Platform Module Ownership	50
1.14.5 Enabling the Trusted Platform Module	51
1.14.6 Assuming Trusted Platform Module Ownership	51
1.14.7 Recovery Procedures	52
1.14.8 Clearing Trusted Platform Module Ownership	53
1.14.9 Software Support	54
2 Technical Reference	55
2.1 Introduction	55
2.2 Memory Resources	55
2.2.1 Addressable Memory	55
2.2.2 Memory Map	57
2.3 DMA Channels	57
2.4 Fixed I/O Map	58
2.5 PCI Configuration Space Map	59
2.6 Interrupts	60
2.7 PCI Conventional Interrupt Routing Map	61
2.8 Connectors	63
2.8.1 Back Panel Connectors	64
2.8.2 Component-side Connectors	66
2.9 Jumper Block	77
2.10 Mechanical Considerations	78
2.10.1 D915GAV Board Form Factor	78
2.10.2 D915GAG Board Form Factor	79
2.10.3 I/O Shield	80
2.11 Electrical Considerations	81
2.11.1 DC Loading	81
2.11.2 Add-in Board Considerations	81
2.11.3 Fan Connector Current Capability	82
2.11.4 Power Supply Considerations	82
2.12 Thermal Considerations	83
2.13 Reliability	85
2.14 Environmental	86
2.15 Regulatory Compliance	87
2.15.1 Safety Regulations	87
2.15.2 EMC Regulations	87
2.15.3 European Union Declaration of Conformity Statement	88
2.15.4 Product Ecology Statements	89
2.15.5 Product Certification Markings (Board Level)	90
3 Overview of BIOS Features	91
3.1 Introduction	91
3.2 BIOS Flash Memory Organization	92
3.3 Resource Configuration	92
3.3.1 PCI Autoconfiguration	92
3.3.2 PCI IDE Support	92
3.4 System Management BIOS (SMBIOS)	93
3.5 Legacy USB Support	93
3.6 BIOS Updates	94
3.6.1 Language Support	94
3.6.2 Custom Splash Screen	94
3.7 Boot Options	95
3.7.1 CD-ROM Boot	95
3.7.2 Network Boot	95
3.7.3 Booting Without Attached Devices	95
3.7.4 Changing the Default Boot Device During POST	95
3.8 Fast Booting Systems with Intel Rapid BIOS Boot	96
3.8.1 Peripheral Selection and Configuration	96
3.8.2 Intel Rapid BIOS Boot	96
3.9 BIOS Security Features	97
4 Error Messages and Beep Codes	99
4.1 BIOS Error Messages	99
4.2 Port 80h POST Codes	101
4.3 Bus Initialization Checkpoints	105
4.4 Speaker	106

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Intel Desktop Board D915GAV/D915GAG Technical Product Specification

2.4

Fixed I/O Map

Table 15.

I/O Map

Address (hex)

Size

Description

0000 - 00FF

256 bytes

Used by the Desktop Board D915GAV/D915GAG.

Refer to

the ICH6 data sheet for dynamic addressing information.

0170 - 0177

8 bytes

Secondary Parallel ATA IDE channel command block

01F0 - 01F7

8 bytes

Primary Parallel ATA IDE channel command block

0228 - 022F

(Note 1)

8 bytes

LPT3

0278 - 027F

(Note 1)

8 bytes

LPT2

02E8 - 02EF

(Note 1)

8 bytes

COM4

02F8 - 02FF

(Note 1)

8 bytes

COM2

0374 - 0377

4 bytes

Secondary Parallel ATA IDE channel control block

0377, bits 6:0

7 bits

Secondary IDE channel status port

0378 - 037F

8 bytes

LPT1

03E8 - 03EF

8 bytes

COM3

03F0 - 03F5

6 bytes

Diskette channel

03F4 – 03F7

1 byte

Primary Parallel ATA IDE channel control block

03F8 - 03FF

8 bytes

COM1

04D0 - 04D1

2 bytes

Edge/level triggered PIC

LPTn + 400

8 bytes

ECP port, LPTn base address + 400h

0CF8 - 0CFB

(Note 2)

4 bytes

PCI Conventional bus configuration address register

0CF9

(Note 3)

1 byte

Reset control register

0CFC - 0CFF

4 bytes

PCI Conventional bus configuration data register

FFA0 - FFA7

8 bytes

Primary Parallel ATA IDE bus master registers

FFA8 - FFAF

8 bytes

Secondary Parallel ATA IDE bus master registers

Notes:

Default, but can be changed to another address range

Dword access only

Byte access only

NOTE

Some additional I/O addresses are not available due to ICH6 address aliassing.

The ICH6 data

sheet provides more information on address aliassing.

For information about

Refer to

Obtaining the ICH6 data sheet

Section 1.4, page 19