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Intel D925XECV2 Product Specification - Page 62

Table 16., PCI Interrupt Routing Map

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Intel Desktop Boards D925XECV2/D925XEBC2 Technical Product Specification Table 16. PCI Interrupt Routing Map PCI Interrupt Source PIRQA IEEE-1394a controller PCI bus connector 1 PCI bus connector 2 PCI bus connector 3 (Note) PCI bus connector 4 (Note) INTD Note: Not present on the D925XEBC2. PIRQB INTA INTC ICH6-R PIRQ Signal Name PIRQC PIRQD PIRQE PIRQF INTA INTB INTB INTA INTD INTC INTA INTB INTC PIRQG INTB INTA INTD PIRQH INTC INTD NOTE In PIC mode, the ICH6-R can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 15 for the allocation of PIRQ lines to IRQ signals in APIC mode. PCI interrupt assignments to the USB ports, Serial ATA ports, and PCI Express ports are dynamic. 62

Section	Page
Intel® Desktop Boards D925XECV2/D925XEBC2 Technical Product Specification	1
Revision History / Disclaimer	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Other Common Notation	4
Contents	5
1 Product Description	11
1.1 PCI Bus Terminology Change	11
1.2 Board Differences	11
1.3 Overview	12
1.3.1 Feature Summary	12
1.3.2 Manufacturing Options	13
1.3.3 Board Layouts	14
1.3.4 Block Diagram	18
1.4 Online Support	19
1.5 Processor	19
1.6 System Memory	20
1.6.1 Memory Configurations	21
1.7 Intel® 925XE Chipset	25
1.7.1 USB	25
1.7.2 IDE Support	25
1.7.3 Real-Time Clock, CMOS SRAM, and Battery	28
1.8 PCI Express Connectors	28
1.9 Auxiliary Power (AUX PWR) Output Connector	28
1.10 I/O Controller	29
1.10.1 Serial Port	29
1.10.2 Parallel Port	29
1.10.3 Diskette Drive Controller	30
1.10.4 Keyboard and Mouse Interface	30
1.11 Audio Subsystem	31
1.11.1 Audio Subsystem Software	31
1.11.2 Audio Connectors	31
1.11.3 8-Channel (7.1) Audio Subsystem	32
1.11.4 6-Channel (5.1) Audio Subsystem	34
1.12 LAN Subsystem	35
1.12.1 Marvell Yukon 88E8050 PCI Express 1.0a Integrated MAC/PHY Gigabit Ethernet Controller	35
1.12.2 RJ-45 LAN Connector with Integrated LEDs	35
1.12.3 Alert Standard Format (ASF) Support	36
1.12.4 LAN Subsystem Software	36
1.13 Hardware Management Subsystem	37
1.13.1 Hardware Monitoring and Fan Control ASIC	37
1.13.2 Thermal Monitoring	38
1.13.3 Fan Monitoring	40
1.13.4 Chassis Intrusion and Detection	40
1.14 Power Management	40
1.14.1 ACPI	40
1.14.2 Hardware Support	43
1.15 Trusted Platform Module (Optional)	47
1.15.1 System Requirements	47
1.15.2 Warning of Potential Data Loss	47
1.15.3 Security Precautions	48
1.15.4 Trusted Platform Module Ownership	49
1.15.5 Enabling the Trusted Platform Module	50
1.15.6 Assuming Trusted Platform Module Ownership	50
1.15.7 Recovery Procedures	51
1.15.8 Clearing Trusted Platform Module Ownership	52
1.15.9 Software Support	53
2 Technical Reference	55
2.1 Introduction	55
2.2 Memory Resources	55
2.2.1 Addressable Memory	55
2.2.2 Memory Map	57
2.3 DMA Channels	57
2.4 Fixed I/O Map	58
2.5 PCI Configuration Space Map	59
2.6 Interrupts	60
2.7 PCI Conventional Interrupt Routing Map	61
2.8 Connectors	63
2.8.1 Back Panel Connectors	63
2.8.2 Component-side Connectors	68
2.9 Jumper Block	80
2.10 Mechanical Considerations	81
2.10.1 D925XECV2 Form Factor	81
2.10.2 D925XEBC2 Form Factor	82
2.10.3 I/O Shield	83
2.11 Electrical Considerations	85
2.11.1 DC Loading	85
2.11.2 Add-in Board Considerations	85
2.11.3 Fan Connector Current Capability	86
2.11.4 Power Supply Considerations	86
2.12 Thermal Considerations	87
2.13 Reliability	89
2.14 Environmental	90
2.15 Regulatory Compliance	91
2.15.1 Safety Regulations	91
2.15.2 EMC Regulations	91
2.15.3 European Union Declaration of Conformity Statement	92
2.15.4 Product Ecology Statements	93
2.15.5 Product Certification Markings (Board Level)	94
3 Overview of BIOS Features	95
3.1 Introduction	95
3.2 BIOS Flash Memory Organization	96
3.3 Resource Configuration	96
3.3.1 PCI Autoconfiguration	96
3.3.2 PCI IDE Support	96
3.4 System Management BIOS (SMBIOS)	97
3.5 Legacy USB Support	97
3.6 BIOS Updates	98
3.6.1 Language Support	98
3.6.2 Custom Splash Screen	98
3.7 Boot Options	99
3.7.1 CD-ROM Boot	99
3.7.2 Network Boot	99
3.7.3 Booting Without Attached Devices	99
3.7.4 Changing the Default Boot Device During POST	99
3.8 Fast Booting Systems with Intel® Rapid BIOS Boot	100
3.8.1 Peripheral Selection and Configuration	100
3.8.2 Intel Rapid BIOS Boot	100
3.9 BIOS Security Features	101
4 Error Messages and Beep Codes	103
4.1 BIOS Error Messages	103
4.2 Port 80h POST Codes	105
4.3 Bus Initialization Checkpoints	109
4.4 Speaker	110