Intel Pga478 Data Sheet - Page 12

Intel

®

Celeron

®

Processor 1.66 GHz/1.83 GHz—Low Power Features

Intel

®

Celeron

®

Processor 1.66 GHz/1.83 GHz

DS

January 2007

12

Order Number: 315876-002

2.1.1.3

C1/MWAIT Powerdown State

MWAIT is a low power state entered when the processor core executes the MWAIT

instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state

except that there is an additional event that can cause the processor core to return to

the C0 state: the Monitor event. Refer to the

Intel® 64 and IA-32 Architectures

Software Developer's Manuals

in

Volume 3A/3B: System Programming Guide

for more

information.

2.1.2

Package Low Power States

The following sections describe all package level low power states for the Intel

®

Celeron

®

Processor 1.66 GHz/1.83 GHz.

2.1.2.1

Normal State

This is the normal operating state for the processor. Intel

®

Celeron

®

Processor 1.66

GHz/1.83 GHz enters the Normal state when its core is in the Normal, AutoHALT, or

MWAIT state.

2.1.2.2

Stop-Grant State

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20

bus clocks after the response phase of the processor-issued Stop Grant Acknowledge

special bus cycle. Once the STPCLK# pin has been asserted, the Intel

®

Celeron

®

Processor 1.66 GHz/1.83 GHz, the processor core must be in the Stop Grant state

before the deassertion of STPCLK#.

Since the AGTL+ signal pins receive power from the system bus, these pins should not

be driven (allowing the level to return to V

CCP

) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the system bus

should be driven to the inactive state.

BINIT# is not serviced while the processor is in Stop-Grant state. The event is latched

and can be serviced by software upon exit from the Stop Grant state.

RESET# causes the processor to immediately initialize itself, but the processor stays in

Stop-Grant state. A transition back to the Normal state occurs with the de-assertion of

the STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state,

STPCLK# should only be deasserted one or more bus clocks after the deassertion of

SLP#.

A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop

on the system bus A transition to the Sleep state occurs with the assertion of the SLP#

signal.

While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] is latched by the

processor, and only serviced when the processor returns to the Normal state. Only one

occurrence of each event is recognized upon return to the Normal state.

While in Stop-Grant state, the processor processes snoops on the system bus and it

latches interrupts delivered on the system bus.

The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is

asserted if there is any pending interrupt latched within the processor. Pending

interrupts that are blocked by the EFLAGS.IF bit being clear still causes assertion of

PBE#. Assertion of PBE# indicates to system logic that it should return the processor to

the Normal state.

Section	Page
Intel® Celeron® Processor 1.66 GHz/ 1.83 GHz	1
Contents	3
Figures	3
Tables	3
Revision History	5
1.0 Introduction	6
Note: The term AGTL+ is used to refer to Assisted GTL+ signaling technology on the processor.	7
1.1 Terminology	7
Table 1. Terminology (Sheet 1 of 2)	7
1.2 References	8
Table 2. References	8
1.3 State of Data	9
Note: All references to the Intel® Celeron® Processor 1.66 GHz/1.83 GHz in this document apply to the Intel® Celeron® Processor 1.66 GHz/1.83 GHz only, unless otherwise specified.	9
2.0 Low Power Features	10
2.1 Clock Control and Low Power States	10
Figure 1. Package-Level Low Power States	10
Figure 2. Core Low Power States	11
2.1.1 Core Low Power States	11
2.1.1.1 C0 State - Normal State	11
2.1.1.2 C1/AutoHALT Powerdown State	11
2.1.1.3 C1/MWAIT Powerdown State	12
2.1.2 Package Low Power States	12
2.1.2.1 Normal State	12
2.1.2.2 Stop-Grant State	12
2.1.2.3 Stop Grant Snoop State	13
2.1.2.4 Sleep State	13
2.2 Enhanced Intel® SpeedStep® Technology (EIST)	13
2.3 Extended Halt State (C1E)	13
Note: The Extended HALT (C1E) state must be enabled for the processor to remain within its specifications.	13
3.0 Electrical Specifications	15
3.1 Front Side Bus and GTLREF	15
3.2 Power and Ground Pins	15
3.3 Decoupling Guidelines	15
3.3.1 VCC Decoupling	15
3.3.2 FSB AGTL+ Decoupling	16
3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking	16
3.4 Voltage Identification and Power Sequencing	16
Table 3. Intel® Celeron® Processor 1.66 GHz/1.83 GHz VID Map (Sheet 1 of 3)	16
3.5 Catastrophic Thermal Protection	18
3.6 Signal Terminations and Unused Pins	18
Note: The TEST1 and TEST2 pins have unique signal termination requirements. It is mandatory that the TEST2 pin have a 51 W +/-5% pull down resistor to Vss. Please refer to Table 11 for details.	18
3.7 FSB Frequency Select Signals (BSEL[2:0])	18
Table 4. BSEL[2:0] Encoding for BCLK Frequency	18
3.8 FSB Signal Groups	19
Table 5. FSB Pin Groups	19
3.9 CMOS Signals	20
3.10 Maximum Ratings	20
Table 6. Processor DC Absolute Maximum Ratings	20
3.11 Processor DC Specifications	20
Note: The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise.	20
Table 7. Voltage and Current Specifications for the Intel® Celeron® Processor 1.66 GHz/1.83 GHz	21
Figure 3. Active VCC and ICC Load Line for Intel® Celeron® Processor 1.66 GHz/1.83 GHz	22
Table 8. AGTL+ Signal Group DC Specifications (Sheet 1 of 2)	22
Table 9. CMOS Signal Group DC Specifications	23
Table 10. Open Drain Signal Group DC Specifications	24
4.0 Package Mechanical Specifications and Pin Information	25
4.1 Package Mechanical Specifications	25
4.1.1 Package Mechanical Drawings	25
Figure 4. Micro-FCPGA Package Top and Bottom Views	25
Figure 5. Micro-FCPGA Processor Package Drawing (Sheet 1)	26
Figure 6. Micro-FCPGA Processor Package Drawing (Sheet 2)	27
4.1.2 Processor Component Keep-Out Zones	27
4.1.3 Package Loading Specifications	28
4.1.4 Processor Mass Specifications	28
4.2 Processor Pin-Out and Pin List	28
Figure 7. The Coordinates of the Processor Pins as Viewed From the Top of the Package	29
4.2.1 Alphabetical Signals Reference	30
Table 11. Signal Description (Sheet 1 of 7)	30
Table 12. Quad-Pumped Signal Groups	32
Table 13. DINV[3:0]# Assignment To Data Bus	32
Table 14. Alphabetical Signal Listing (Sheet 1 of 12)	37
Table 15. Alphabetical Pin Listing (Sheet 1 of 12)	49
5.0 Thermal Specifications and Design Considerations	61
Table 16. Power Specifications for the Intel® Celeron® Processor 1.66 GHz/1.83 GHz (Sheet 1 of 2)	61
5.1 Thermal Specifications	62
5.1.1 Thermal Diode	62
Note: The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals, does not...	62
Table 17. Thermal Diode Interface	63
Table 18. Thermal “Diode” Parameters using Diode Mode	63
5.1.2 Thermal Diode Offset	64
Table 19. Thermal “Diode” ntrim and Diode Correction Toffset	64
5.1.3 Intel® Thermal Monitor	64
Note: The Intel thermal monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications.	64
Note: Intel recommends both Thermal Monitor 1 (TM1) and Thermal Monitor 2 (TM2) be always enabled on Intel® Celeron® Processor 1.66 GHz/1.83 GHz.	64
Note: The Intel® Celeron® Processor 1.66 GHz/1.83 GHz only supports TM2 initiated voltage/ frequency transitions. Intel® Celeron...	65
Note: PROCHOT# is not asserted when the processor is in the Stop Grant, and Sleep, low power states (internal clocks stopped), h...	65
5.1.4 Digital Thermal Sensor	66
5.1.5 Out of Specification Detection	66
5.1.6 PROCHOT# Signal Pin	66
5.1.7 FORCEPR# Signal Pin	67

Intel Pga478 Data Sheet - Page 12

Package Low Power States

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