Intel Pga478 Data Sheet - Page 23

Intel

®

Celeron

®

Processor 1.66 GHz/1.83 GHz

January 2007

DS

Order Number: 315876-002

23

Electrical Specifications—Intel

®

Celeron

®

Processor 1.66 GHz/1.83 GHz

.

V

IH

Input High Voltage

GTLREF+100

V

CCP

V

CCP

+100

mV

3,6

V

IL

Input Low Voltage

-100

0

GTLREF-100

mV

2,4

V

OH

Output High Voltage

V

CCP

- 100

V

CCP

mV

6

R

TT

Termination Resistance

45

50

55

Ω

7,10

R

ON

Buffer On Resistance

22.3

25.5

28.7

W

5

I

LI

Input Leakage Current

± 100

μA

8

Cpad

Pad Capacitance

1.8

2.3

2.75

pF

9

Table 9.

CMOS Signal Group DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

1

V

CCP

I/O Voltage

0.997

1.05

1.102

V

V

IL

Input Low Voltage

CMOS

-0.1

0

0.33

V

2, 3

V

IH

Input High Voltage

0.7

1.05

1.20

V

2

V

OL

Output Low Voltage

-0.1

0

0.11

V

2

V

OH

Output High Voltage

0.9

V

CCP

1.2

V

2

I

OL

Output Low Current

1.3

4.1

mA

4

I

OH

Output High Current

1.3

4.1

mA

5

I

LI

Leakage Current

± 100

μA

6

Cpad1

Pad Capacitance

1.8

2.3

2.75

pF

7

Cpad2

Pad Capacitance for CMOS

Input

0.95

1.2

1.45

pF

8

Notes:

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

The V

CCP

referred to in these specifications refers to instantaneous V

CCP

.

3.

Refer to the processor I/O Buffer Models for I/V characteristics.

4.

Measured at 0.1*V

CCP

.

5.

Measured at 0.9*V

CCP

.

6.

For Vin between 0V and V

CCP

. Measured when the driver is tristated.

7.

Cpad1 includes die capacitance only for PWRGOOD. No package parasitics are included.

8.

Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.

Table 8.

AGTL+ Signal Group DC Specifications (Sheet 2 of 2)

Notes:

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

V

IL

is defined as the maximum voltage level at a receiving agent that is interpreted as a logical low

value.

3.

V

IH

is defined as the minimum voltage level at a receiving agent that is interpreted as a logical high

value.

4.

V

IH

and V

OH

may experience excursions above V

CCP

. However, input signal drivers must comply with

the signal quality specifications.

5.

This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.

Measured at 0.31*V

CCP

. R

ON

(min) = 0.38*R

TT

,

R

ON

(typ) = 0.45*R

TT

,

R

ON

(max) = 0.52*R

TT

.

6.

GTLREF should be generated from V

CCP

with a 1% tolerance resistor divider. The V

CCP

referred to in

these specifications is the instantaneous V

CCP

.

7.

R

TT

is the on-die termination resistance measured at V

OL

of the AGTL+ output driver. Measured at

0.31*V

CCP

. R

TT

is connected to V

CCP

on die. Refer to processor I/O buffer models for I/V

characteristics.

8.

Specified with on die R

TT

and R

ON

are turned off.

9.

Cpad includes die capacitance only. No package parasitics are included.

10.

R

TT

for PREQ# is between 1.5k

Ω

and 6.0k

Ω

Section	Page
Intel® Celeron® Processor 1.66 GHz/ 1.83 GHz	1
Contents	3
Figures	3
Tables	3
Revision History	5
1.0 Introduction	6
Note: The term AGTL+ is used to refer to Assisted GTL+ signaling technology on the processor.	7
1.1 Terminology	7
Table 1. Terminology (Sheet 1 of 2)	7
1.2 References	8
Table 2. References	8
1.3 State of Data	9
Note: All references to the Intel® Celeron® Processor 1.66 GHz/1.83 GHz in this document apply to the Intel® Celeron® Processor 1.66 GHz/1.83 GHz only, unless otherwise specified.	9
2.0 Low Power Features	10
2.1 Clock Control and Low Power States	10
Figure 1. Package-Level Low Power States	10
Figure 2. Core Low Power States	11
2.1.1 Core Low Power States	11
2.1.1.1 C0 State - Normal State	11
2.1.1.2 C1/AutoHALT Powerdown State	11
2.1.1.3 C1/MWAIT Powerdown State	12
2.1.2 Package Low Power States	12
2.1.2.1 Normal State	12
2.1.2.2 Stop-Grant State	12
2.1.2.3 Stop Grant Snoop State	13
2.1.2.4 Sleep State	13
2.2 Enhanced Intel® SpeedStep® Technology (EIST)	13
2.3 Extended Halt State (C1E)	13
Note: The Extended HALT (C1E) state must be enabled for the processor to remain within its specifications.	13
3.0 Electrical Specifications	15
3.1 Front Side Bus and GTLREF	15
3.2 Power and Ground Pins	15
3.3 Decoupling Guidelines	15
3.3.1 VCC Decoupling	15
3.3.2 FSB AGTL+ Decoupling	16
3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking	16
3.4 Voltage Identification and Power Sequencing	16
Table 3. Intel® Celeron® Processor 1.66 GHz/1.83 GHz VID Map (Sheet 1 of 3)	16
3.5 Catastrophic Thermal Protection	18
3.6 Signal Terminations and Unused Pins	18
Note: The TEST1 and TEST2 pins have unique signal termination requirements. It is mandatory that the TEST2 pin have a 51 W +/-5% pull down resistor to Vss. Please refer to Table 11 for details.	18
3.7 FSB Frequency Select Signals (BSEL[2:0])	18
Table 4. BSEL[2:0] Encoding for BCLK Frequency	18
3.8 FSB Signal Groups	19
Table 5. FSB Pin Groups	19
3.9 CMOS Signals	20
3.10 Maximum Ratings	20
Table 6. Processor DC Absolute Maximum Ratings	20
3.11 Processor DC Specifications	20
Note: The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise.	20
Table 7. Voltage and Current Specifications for the Intel® Celeron® Processor 1.66 GHz/1.83 GHz	21
Figure 3. Active VCC and ICC Load Line for Intel® Celeron® Processor 1.66 GHz/1.83 GHz	22
Table 8. AGTL+ Signal Group DC Specifications (Sheet 1 of 2)	22
Table 9. CMOS Signal Group DC Specifications	23
Table 10. Open Drain Signal Group DC Specifications	24
4.0 Package Mechanical Specifications and Pin Information	25
4.1 Package Mechanical Specifications	25
4.1.1 Package Mechanical Drawings	25
Figure 4. Micro-FCPGA Package Top and Bottom Views	25
Figure 5. Micro-FCPGA Processor Package Drawing (Sheet 1)	26
Figure 6. Micro-FCPGA Processor Package Drawing (Sheet 2)	27
4.1.2 Processor Component Keep-Out Zones	27
4.1.3 Package Loading Specifications	28
4.1.4 Processor Mass Specifications	28
4.2 Processor Pin-Out and Pin List	28
Figure 7. The Coordinates of the Processor Pins as Viewed From the Top of the Package	29
4.2.1 Alphabetical Signals Reference	30
Table 11. Signal Description (Sheet 1 of 7)	30
Table 12. Quad-Pumped Signal Groups	32
Table 13. DINV[3:0]# Assignment To Data Bus	32
Table 14. Alphabetical Signal Listing (Sheet 1 of 12)	37
Table 15. Alphabetical Pin Listing (Sheet 1 of 12)	49
5.0 Thermal Specifications and Design Considerations	61
Table 16. Power Specifications for the Intel® Celeron® Processor 1.66 GHz/1.83 GHz (Sheet 1 of 2)	61
5.1 Thermal Specifications	62
5.1.1 Thermal Diode	62
Note: The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals, does not...	62
Table 17. Thermal Diode Interface	63
Table 18. Thermal “Diode” Parameters using Diode Mode	63
5.1.2 Thermal Diode Offset	64
Table 19. Thermal “Diode” ntrim and Diode Correction Toffset	64
5.1.3 Intel® Thermal Monitor	64
Note: The Intel thermal monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications.	64
Note: Intel recommends both Thermal Monitor 1 (TM1) and Thermal Monitor 2 (TM2) be always enabled on Intel® Celeron® Processor 1.66 GHz/1.83 GHz.	64
Note: The Intel® Celeron® Processor 1.66 GHz/1.83 GHz only supports TM2 initiated voltage/ frequency transitions. Intel® Celeron...	65
Note: PROCHOT# is not asserted when the processor is in the Stop Grant, and Sleep, low power states (internal clocks stopped), h...	65
5.1.4 Digital Thermal Sensor	66
5.1.5 Out of Specification Detection	66
5.1.6 PROCHOT# Signal Pin	66
5.1.7 FORCEPR# Signal Pin	67

Intel Pga478 Data Sheet - Page 23

Table 9., CMOS Signal Group DC Specifications, Table 8., AGTL+ Signal Group DC Specifications Sheet

Page 23 highlights