Intel Pga478 Data Sheet - Page 20

Intel® Celeron® Processor 1.66 GHz/1.83 GHz-Electrical Specifications 3.9 3.10 Table 6. 3.11 Note: CMOS Signals CMOS input signals are shown in Table 5. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for at least three BCLKs in order for the processor to recognize them. See Section 3.11 for the DC for the CMOS signal groups. Maximum Ratings Table 6 lists the processor's maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from Electro-Static Discharge (ESD), one should always take precautions to avoid high static voltages of electric fields. Processor DC Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes TSTORAGE Processor storage temperature -40 85 °C 2 VCC Any processor supply voltage with respect to VSS -0.3 1.6 V 1 VinAGTL+ AGTL+ buffer DC input voltage with respect to VSS -0.1 1.6 V 1, 2 VinAsynch_CMOS CMOS buffer DC input voltage with respect to VSS -0.1 1.6 V 1, 2 Notes: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect the long term reliability of the device. For functional operation, please refer to the processor case temperature specifications. Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 5 for the pin signal definitions and signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 8. DC specifications for the CMOS group are listed in Table 9. Table 7 through Table 10 list the DC specifications for the Intel® Celeron® Processor 1.66 GHz/1.83 GHz and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest and lowest core operating frequencies supported on a particular processor. Active mode load line specifications apply in all states. VCC,BOOT is the default voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified otherwise, all specifications for the Intel® Celeron® Processor 1.66 GHz/1.83 GHz are at Tjunction = 100 °C. Care should be taken to read all notes associated with each parameter. The Intel® Celeron® Processor 1.66 GHz/1.83 GHz does not support Enhanced Intel SpeedStep® Technology (EIST), therefore HFM and LFM transitions are not supported. Intel® Celeron® Processor 1.66 GHz/1.83 GHz DS 20 January 2007 Order Number: 315876-002