Intel X3350 Design Guide - Page 51

Thermal Specifications 6.2.3 6.3 6.3.1 6.3.1.1 PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that PROCHOT# will only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the appropriate platform design guide and for details on implementing the bi-directional PROCHOT# feature. THERMTRIP# Signal Regardless of whether or not Adaptive Thermal Monitor is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (see the THERMTRIP# definition in the Datasheet). At this point, the THERMTRIP# signal will go active and stay active as described in the Datasheet. THERMTRIP# activation is independent of processor activity. If THERMTRIP# is asserted, processor core voltage (VCC) must be removed within the timeframe defined in the Datasheet. The temperature at which THERMTRIP# asserts is not user configurable and is not software visible. Platform Environment Control Interface (PECI) Introduction The Platform Environment Control Interface (PECI) is a one-wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices. The processor implements a PECI interface to allow communication of processor thermal and other information to other devices on the platform. The processor provides a digital thermal sensor (DTS) on each core for fan speed control. The DTS is calibrated at the factory to provide a digital representation of processor temperature relative PROCHOT# assertion. Instantaneous temperature readings from the DTS are available via the IA32_TEMP_STATUS MSR; averaged DTS values are read via the PECI interface. The PECI physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a logic '0' or logic '1'. PECI also includes variable data transfer rate established with every message. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. Bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information. Fan Speed Control with Digital Thermal Sensor Fan speed control solutions use a value stored in the static variable, TCONTROL. The DTS temperature data which is delivered over PECI (in response to a GetTemp0() command) is compared to this TCONTROL reference. The DTS temperature is reported as a relative value versus an absolute value. The temperature reported over PECI is Intel® Xeon® Processor C5500/C3500 Series and LGA1366 Socket Thermal/Mechanical Design Guide 51 August 2010 Order Number: 323107-002US